scc

commit e62c7cfed2db41bfab11335f18a4d5df9efa3dc2
parent 2aa2616eac2c3be102c7cdfbbb8bc1379fcd7f81
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Sun, 17 Dec 2017 20:22:00 +0100

[as-z80] Add I and R load operations

Diffstat:
M
as/target/gen.awk
 | 
4
++++
M
as/target/x80/x80.dat
 | 
4
++++

2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/as/target/gen.awk b/as/target/gen.awk
@@ -89,6 +89,8 @@ function str2args(s, args, i, out, n)
 			out = out "AREG_QCLASS"
 		} else if (match(a, /^reg_r/)) {
 			out = out "AREG_RCLASS"
+		} else if (match(a, /^regR/)) {
+			out = out "AREG_R"
 		} else if (match(a, /^regA/)) {
 			out = out "AREG_A"
 		} else if (match(a, /^indir_DE/)) {
@@ -107,6 +109,8 @@ function str2args(s, args, i, out, n)
 			out = out "AREG_IY"
 		} else if (match(a, /^dir/)) {
 			out = out "ADIRECT"
+		} else if (match(a, /^regI/)) {
+			out = out "AREG_I"
 		} else if (match(a, /^sym/)) {
 			out = out "ASYM"
 		} else if (match(a, /^string/)) {
diff --git a/as/target/x80/x80.dat b/as/target/x80/x80.dat
@@ -106,6 +106,10 @@ LD	indir_BC,regA	1	0x2	noargs	Z80,R800,GB80
 LD	indir_DE,regA	1	0x12	noargs	Z80,R800,GB80
 LD	dir,regA	3	0x32	dir	Z80,R800,GB80
 
+LD	regA,regI	2	0xed,0x57	noargs	Z80,R800
+LD	regA,regR	2	0xed,0x57	noargs	Z80,R800
+LD	regI,regA	2	0xed,0x47	noargs	Z80,R800
+LD	regR,regA	2	0xed,0x4f	noargs	Z80,R800
 
 # 16 bit load group
 LD	reg_dd,imm16	3	0x01	r16_imm16	Z80,R800,GB80