scc

commit 2aa2616eac2c3be102c7cdfbbb8bc1379fcd7f81
parent 6847ff0a060948214fd8b197436f16cc0c5579db
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Sun, 17 Dec 2017 20:13:32 +0100

[as-z80] Add indirect BC and DE load instructions

Diffstat:
M
as/target/gen.awk
 | 
4
++++
M
as/target/x80/proc.h
 | 
6
++++--
M
as/target/x80/x80.dat
 | 
9
+++++++++

3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/as/target/gen.awk b/as/target/gen.awk
@@ -91,6 +91,10 @@ function str2args(s, args, i, out, n)
 			out = out "AREG_RCLASS"
 		} else if (match(a, /^regA/)) {
 			out = out "AREG_A"
+		} else if (match(a, /^indir_DE/)) {
+			out = out "AINDER_DE"
+		} else if (match(a, /^indir_BC/)) {
+			out = out "AINDER_BC"
 		} else if (match(a, /^indir_HL/)) {
 			out = out "AINDER_HL"
 		} else if (match(a, /^regSP/)) {
diff --git a/as/target/x80/proc.h b/as/target/x80/proc.h
@@ -35,10 +35,12 @@ enum args {
 	AREG_DDCLASS, /* register class for BC, DE, HL and SP */
 	AREG_QQCLASS, /* register class for BC, DE, HL and AF */
 
-	AINDEX_IX,
-	AINDEX_IY,
+	AINDEX_IX,    /* (IX+d) */
+	AINDEX_IY,    /* (IX+d) */
 
 	AINDER_HL,    /* (HL) */
+	AINDER_DE,    /* (DE) */
+	AINDER_BC,    /* (BC) */
 };
 
 extern int rclass(int reg);
diff --git a/as/target/x80/x80.dat b/as/target/x80/x80.dat
@@ -98,6 +98,15 @@ LD	indir_HL,imm8	2	0x36	imm8	Z80,R800,GB80
 LD	idx_IX,imm8	3	0xdd,0x36	idx_imm8	Z80,R800
 LD	idx_IY,imm8	3	0xfd,0x36	idx_imm8	Z80,R800
 
+LD	regA,indir_BC	1	0x0a	noargs	Z80,R800,GB80
+LD	regA,indir_DE	1	0x1a	noargs	Z80,R800,GB80
+LD	regA,dir	3	0x3a	dir	Z80,R800,GB80
+
+LD	indir_BC,regA	1	0x2	noargs	Z80,R800,GB80
+LD	indir_DE,regA	1	0x12	noargs	Z80,R800,GB80
+LD	dir,regA	3	0x32	dir	Z80,R800,GB80
+
+
 # 16 bit load group
 LD	reg_dd,imm16	3	0x01	r16_imm16	Z80,R800,GB80
 LD	regIX,imm16	4	0xdd,0x21	imm16	Z80,R800