qbe

commit c656c48f04aff067b7addd8d1c40935f6bf3acca
parent c5769f62b4912e429a332c9aa0bead3a383fe966
Author: Quentin Carbonneaux <quentin@c9x.me>
Date:   Tue, 15 Mar 2022 14:10:14 +0100

fix register count in riscv argregs

Diffstat:
M
rv64/abi.c
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rv64/abi.c b/rv64/abi.c
@@ -82,7 +82,7 @@ rv64_argregs(Ref r, int p[2])
 	nfp = (r.val >> 8) & 15;
 	t5 = (r.val >> 12) & 1;
 	if (p) {
-		p[0] = ngp;
+		p[0] = ngp + t5;
 		p[1] = nfp;
 	}
 	b = 0;