qbe

commit c5259db2c45e60db6b7468f9d24dd66882da6fd5
parent 3ad28f1560132688e5a1e951c2152708b2992ee3
Author: Quentin Carbonneaux <quentin.carbonneaux@yale.edu>
Date:   Fri, 20 Nov 2015 15:49:10 -0500

avoid having conflicting hints in rega

Diffstat:
M
lisc/rega.c
 | 
19
++++++++++++++-----

1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/lisc/rega.c b/lisc/rega.c
@@ -28,6 +28,17 @@ hint(int t)
 	return &tmp[phicls(t, tmp)].hint.r;
 }
 
+static void
+sethint(int t, int r)
+{
+	ulong m;
+
+	m = tmp[phicls(t, tmp)].hint.m;
+	if (*hint(t) == -1)
+	if (!(BIT(r) & m))
+		*hint(t) = r;
+}
+
 static int
 rfind(RMap *m, int t)
 {
@@ -96,8 +107,7 @@ ralloc(RMap *m, int t)
 					diag("rega: no more regs");
 	}
 	radd(m, t, r);
-	if (*hint(t) == -1)
-		*hint(t) = r;
+	sethint(t, r);
 	return TMP(r);
 }
 
@@ -340,8 +350,7 @@ doblk(Blk *b, RMap *cur)
 			}
 			if (isreg(i->to))
 			if (rtype(i->arg[0]) == RTmp)
-			if (*hint(i->arg[0].val) == -1)
-				*hint(i->arg[0].val) = i->to.val;
+				sethint(i->arg[0].val, i->to.val);
 			/* fall through */
 		default:
 			if (!req(i->to, R)) {
@@ -402,7 +411,7 @@ rega(Fn *fn)
 			break;
 		else {
 			assert(rtype(i->to) == RTmp);
-			*hint(i->to.val) = i->arg[0].val;
+			sethint(i->to.val, i->arg[0].val);
 		}
 
 	/* 2. assign registers following post-order */