commit eefec00c787ec039b8256db13b45c4ea12580650
parent fcdebdcef82eefca5508fcd5eedeb9343e96f437
Author: Roberto Vargas <roberto.vargas@arm.com>
Date: Sun, 14 Oct 2018 15:34:16 +0100
[arch/arm64] Reorder functions in arch.s
Change-Id: I013b86fb64dfe330237ea00f9ac91c22ea584439
Diffstat:
| M | arch/arm64/arch.s | | | 125 | +++++++++++++++++++++++++++++++++++++++---------------------------------------- |
1 file changed, 62 insertions(+), 63 deletions(-)
diff --git a/arch/arm64/arch.s b/arch/arm64/arch.s
@@ -12,36 +12,6 @@ DAIF_DBG = 4
.globl read_rvbar_el3,vectbl,swtch
.align 2
-panic:
- stp x1,x0,[sp,#-16]!
- stp x3,x2,[sp,#-16]!
- stp x5,x4,[sp,#-16]!
- stp x7,x6,[sp,#-16]!
- stp x9,x8,[sp,#-16]!
- stp x11,x10,[sp,#-16]!
- stp x13,x12,[sp,#-16]!
- stp x15,x14,[sp,#-16]!
- stp x17,x16,[sp,#-16]!
- stp x19,x18,[sp,#-16]!
- stp x21,x20,[sp,#-16]!
- stp x23,x22,[sp,#-16]!
- stp x25,x24,[sp,#-16]!
- stp x27,x26,[sp,#-16]!
- stp x29,x28,[sp,#-16]!
- mov x1,sp
- stp x1,x30,[sp,#-16]!
-
- mrs x3,S3_6_C4_C0_6 /* SPSR_R */
- mrs x2,S3_6_C4_C0_3 /* ELR_R */
- stp x3,x2,[sp,#-16]!
-
- mrs x3,S3_6_C6_C0_6 /* FAR_R */
- mrs x2,S3_6_C5_C2_6 /* ESR_R */
- stp x3,x2,[sp,#-16]!
-
- mov x1,sp
- b cpanic
-
enaabt:
msr daifclr,DAIF_ABT
ret
@@ -108,9 +78,35 @@ read_rvbar_el3:
mrs x0,rvbar_el3
ret
-_badtrap:
- adr x0,unexpected
- b panic
+panic:
+ stp x1,x0,[sp,#-16]!
+ stp x3,x2,[sp,#-16]!
+ stp x5,x4,[sp,#-16]!
+ stp x7,x6,[sp,#-16]!
+ stp x9,x8,[sp,#-16]!
+ stp x11,x10,[sp,#-16]!
+ stp x13,x12,[sp,#-16]!
+ stp x15,x14,[sp,#-16]!
+ stp x17,x16,[sp,#-16]!
+ stp x19,x18,[sp,#-16]!
+ stp x21,x20,[sp,#-16]!
+ stp x23,x22,[sp,#-16]!
+ stp x25,x24,[sp,#-16]!
+ stp x27,x26,[sp,#-16]!
+ stp x29,x28,[sp,#-16]!
+ mov x1,sp
+ stp x1,x30,[sp,#-16]!
+
+ mrs x3,S3_6_C4_C0_6 /* SPSR_R */
+ mrs x2,S3_6_C4_C0_3 /* ELR_R */
+ stp x3,x2,[sp,#-16]!
+
+ mrs x3,S3_6_C6_C0_6 /* FAR_R */
+ mrs x2,S3_6_C5_C2_6 /* ESR_R */
+ stp x3,x2,[sp,#-16]!
+
+ mov x1,sp
+ b cpanic
_synchdl:
stp x1,x0,[sp,#-16]!
@@ -143,11 +139,42 @@ _synchdl:
adr x0,outsync
b panic
-outsync:
- .asciz "out of sync"
+swtch:
+ mov sp,x0
+ ldp x1,x0,[sp],#16
+ msr S3_6_C6_C0_6,x1 /* FAR_R */
+ msr S3_6_C5_C2_6,x0 /* ESR_R */
+
+ ldp x1,x0,[sp],#16
+ msr S3_6_C4_C0_6,x1 /* SPSR_R */
+ msr S3_6_C4_C0_3,x0 /* ELR_R */
+
+ ldp xzr,x30,[sp],#16
+ ldp x29,x28,[sp],#16
+ ldp x27,x26,[sp],#16
+ ldp x25,x24,[sp],#16
+ ldp x23,x22,[sp],#16
+ ldp x21,x20,[sp],#16
+ ldp x19,x18,[sp],#16
+ ldp x17,x16,[sp],#16
+ ldp x15,x14,[sp],#16
+ ldp x13,x12,[sp],#16
+ ldp x11,x10,[sp],#16
+ ldp x9,x8,[sp],#16
+ ldp x7,x6,[sp],#16
+ ldp x5,x4,[sp],#16
+ ldp x3,x2,[sp],#16
+ ldp x1,x0,[sp],#16
+ eret
unexpected:
.asciz "unexpected exception"
+outsync:
+ .asciz "out of sync"
+
+_badtrap:
+ adr x0,unexpected
+ b panic
.align 11
vectbl:
@@ -174,31 +201,3 @@ vectbl:
b _badtrap; nop /* IRQ/vIRQ */
b _badtrap; nop /* FIQ/vFIQ */
b _badtrap; nop /* SError/VSError */
-
-swtch:
- mov sp,x0
- ldp x1,x0,[sp],#16
- msr S3_6_C6_C0_6,x1 /* FAR_R */
- msr S3_6_C5_C2_6,x0 /* ESR_R */
-
- ldp x1,x0,[sp],#16
- msr S3_6_C4_C0_6,x1 /* SPSR_R */
- msr S3_6_C4_C0_3,x0 /* ELR_R */
-
- ldp xzr,x30,[sp],#16
- ldp x29,x28,[sp],#16
- ldp x27,x26,[sp],#16
- ldp x25,x24,[sp],#16
- ldp x23,x22,[sp],#16
- ldp x21,x20,[sp],#16
- ldp x19,x18,[sp],#16
- ldp x17,x16,[sp],#16
- ldp x15,x14,[sp],#16
- ldp x13,x12,[sp],#16
- ldp x11,x10,[sp],#16
- ldp x9,x8,[sp],#16
- ldp x7,x6,[sp],#16
- ldp x5,x4,[sp],#16
- ldp x3,x2,[sp],#16
- ldp x1,x0,[sp],#16
- eret
