commit e17ee6612569013d56858cba4c0bb1d4d8d94ea7
parent 1f846556907895e491d5dfeea711b93dc4d38787
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date: Sun, 25 Oct 2020 23:06:31 +0100
os9/arm64: Fix page table allocation
Change-Id: I3bac03ed162022d69beec48e2cee49e9a970f466
Diffstat:
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/os9/arch/arm64/mmu.c b/src/os9/arch/arm64/mmu.c
@@ -138,6 +138,17 @@
int inlowmem = 1;
+static pte_t
+newpage(void)
+{
+ void *bp;
+
+ bp = allocb(1);
+ memset(bp, 0, PAGESIZE);
+
+ return (pte_t) bp;
+}
+
static pte_t *
walker(uintptr_t va)
{
@@ -154,14 +165,13 @@ walker(uintptr_t va)
e = bp[n];
if (e == INVALID) {
- e = (pte_t) allocb(1);
+ e = newpage();
bp[n] = e | TABLE;
barrier(DATA);
}
bp = (pte_t *) MASK(e);
}
- dbg("va = %llx, level=%d, bp=%p, n=%d, e=%llx\n", va, 3, &bp[TINDEX(3, va)], TINDEX(3, va), bp[TINDEX(3, va)]);
return &bp[TINDEX(3, va)];
}
@@ -268,7 +278,7 @@ kernelmap(void)
* FIXME: We are using a full page when
* we only need 16 bytes with 16 byte alignment.
*/
- syswr(TTBR1_EL1, (pte_t) allocb(1));
+ syswr(TTBR1_EL1, newpage());
dbg("TTBR1_EL1=%llx\n", sysrd(TTBR1_EL1));
@@ -281,7 +291,7 @@ kernelmap(void)
void
initmap(void)
{
- pte_t *bp, *tbl;
+ pte_t *bp, tbl;
phyaddr_t pa;
uint64_t tcr;
pte_t attr = CONT | AF(1) | SH(OS) | AP(RDWR) | IDX(DEV) | BLOCK;
@@ -292,11 +302,12 @@ initmap(void)
syswr(TCR_EL1, tcr);
barrier(CODE);
- tbl = bp = allocb(1);
+ tbl = newpage();
+ bp = (pte_t *) tbl;
for (pa = 0; pa < 4*GiB; pa += 1*GiB)
*bp++ = pa | attr;
- syswr(TTBR0_EL1, (uint64_t) tbl);
+ syswr(TTBR0_EL1, tbl);
barrier(DATA);
barrier(CODE);
}