commit bbb8c2725b38f32b71a81dc90480f37acfa338e3
parent a2e973f4892f67b30105c02d9c4571749fb17907
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date: Thu, 26 Aug 2021 07:26:01 +0200
os9/arm64: Remove cache initialization
This work is done by the firmware and it is not needed to
be done by the kernel.
Change-Id: I207473259408871a1fda00fd4e0ea01450e2b897
Diffstat:
5 files changed, 0 insertions(+), 112 deletions(-)
diff --git a/src/os9/arch/arm64/Makefile b/src/os9/arch/arm64/Makefile
@@ -15,7 +15,6 @@ COMMON_OBJS =\
crt.o\
fpu.o\
mmu.o\
- cache.o\
gic.o\
$(SRCDIR)/os9/builtin.o \
diff --git a/src/os9/arch/arm64/arch.h b/src/os9/arch/arm64/arch.h
@@ -23,13 +23,11 @@
extern void main(Mach *);
extern void syswr(int, unsigned long long);
extern unsigned long long sysrd(int);
-extern void invicache(void);
extern void invalltlb(void);
extern void invtlb(uintptr_t);
extern void invdcachesetway(void *);
extern void *outsync(void);
-extern void icache(void);
extern void immu(void);
extern void ifpu(void);
extern void igic(void);
diff --git a/src/os9/arch/arm64/arch.s b/src/os9/arch/arm64/arch.s
@@ -49,12 +49,6 @@ invdcachesetway:
RET
.TEXT
- .GLOBL invicache
-invicache:
- IC IALLU
- RET
-
- .TEXT
.GLOBL inm8
inm8:
LDRB W0,[X0]
diff --git a/src/os9/arch/arm64/cache.c b/src/os9/arch/arm64/cache.c
@@ -1,102 +0,0 @@
-#include <os9/os9.h>
-
-#include "sysreg.h"
-#include "arch.h"
-
-#define NR_LEVELS 7
-
-/* clidr_el1 */
-#define LOC_SHIFT 24
-#define LOC_MASK 0x7
-#define CTYPE_MASK 0x7
-
-/* ccsidr_el1 */
-#define NSETS_SHIFT 13
-#define NSETS_MASK 0x7fff
-#define NWAYS_SHIFT 3
-#define NWAYS_MASK 0x3ff
-#define LINE_MASK 0x7
-
-/* csselr_el1 */
-#define LEVEL_SHIFT 1
-
-
-static unsigned
-log2(unsigned long long v, unsigned width)
-{
- unsigned nbits, i = width;
-
- for (nbits = 0; i-- > 0; nbits++) {
- if ((v & (1ull << i)) != 0)
- break;
- }
- return width - nbits - 1;
-}
-
-static void
-invdcachelvl(unsigned l)
-{
- unsigned long long ccsidr;
- unsigned nsets, nways, size, shift, i, j;
-
- syswr(CSSELR_EL1, l << LEVEL_SHIFT);
- barrier(CODE);
-
- ccsidr = sysrd(CCSIDR_EL1);
- nsets = ((ccsidr >> NSETS_SHIFT) & NSETS_MASK) + 1;
- nways = ((ccsidr >> NWAYS_SHIFT) & NWAYS_MASK) + 1;
- size = (ccsidr & LINE_MASK) + 4;
- shift = 32 - log2(nways, 32);
-
- for (i = 0; i < nways; i++) {
- for (j = 0; j < nsets; j++) {
- uintptr_t addr;
-
- addr = (uintptr_t)i << shift | j << size | l << 1;
- invdcachesetway((void *)addr);
- }
- }
- barrier(DATA);
-}
-
-static void
-invdcache(void)
-{
- unsigned long long clidr;
- unsigned l;
- enum cachetype {
- NOCACHE,
- ICACHE,
- DCACHE,
- HARVARD,
- UNIFIED
- } type;
-
- barrier(DATA);
-
- clidr = sysrd(CLIDR_EL1);
- if (((clidr >> LOC_SHIFT) & LOC_MASK) == 0)
- return;
-
- for (l = 0; l < NR_LEVELS; l++) {
- type = clidr & CTYPE_MASK;
- if (type == NOCACHE || type == ICACHE)
- continue;
-
- invdcachelvl(l);
- clidr >>= 3;
- }
-}
-
-void
-icache(void)
-{
- uint64_t sctlr;
-
- invicache();
- invdcache();
-
- sctlr = sysrd(SCTLR_EL1);
- sctlr |= C | I;
- syswr(SCTLR_EL1, sctlr);
-}
diff --git a/src/os9/arch/arm64/crt.s b/src/os9/arch/arm64/crt.s
@@ -48,7 +48,6 @@ EL1:
BL memset
BL imach
- BL icache
BL immu
BL initmap
BL mmuon
