commit 9eb96ea3f960237a04270b7e359bbd8d17803cc0
parent 80d364faba4f8c8ff8b5aa98228425e95b37de0a
Author: Roberto Vargas <roberto.vargas@arm.com>
Date: Thu, 15 Nov 2018 14:31:25 +0000
[arch/arm64] Autogenerate the sysreg functions
Change-Id: Ia58b12c8e4febca1d88cc34f59fdfa5a607aafc1
Diffstat:
7 files changed, 62 insertions(+), 80 deletions(-)
diff --git a/arch/arm64/.gitignore b/arch/arm64/.gitignore
@@ -0,0 +1,2 @@
+sysreg.h
+sysreg.s
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
@@ -9,6 +9,7 @@ MORECFLAGS = -DUARTBASE=0x1c0c0000 \
ROMOBJS = rom-crt-$(SYS).o \
rom-$(SYS).o \
arch.o \
+ sysreg.o \
$(DLANG) \
$(DRVDIR)/uart.o \
$(SRCDIR)/romfw/builtin.o \
@@ -16,6 +17,7 @@ ROMOBJS = rom-crt-$(SYS).o \
RAMOBJS = ram-crt-$(SYS).o \
ram-$(SYS).o \
arch.o \
+ sysreg.o \
$(DLANG) \
$(DRVDIR)/uart.o \
$(SRCDIR)/ramfw/builtin.o \
@@ -27,6 +29,14 @@ all: $(TARGET)
ram-crt-none.o rom-crt-none.o: crt-none.s
ram-crt-linux.o rom-crt-linux.o: crt-linux.s
+rom-rmode.o: sysreg.h
+
+sysreg.h: sysreg.lst
+ ./gensysreg.sh -h sysreg.lst
+
+sysreg.s: sysreg.lst
+ ./gensysreg.sh -s sysreg.lst
+
$(BINDIR)/romfw.elf: $(ROMOBJS) $(LIBDEP)
$(LD) $(RCODE_LDFLAGS) $(ROMOBJS) $(LIBS) -o $@
@@ -36,6 +46,7 @@ $(BINDIR)/ramfw.elf: $(RAMOBJS) $(LIBDEP)
clean:
rm -f $(TARGET:.bin=.elf)
rm -f $(TARGET:.bin=.tst)
+ rm -f sysreg.h sysreg.s
#
# Rules to verify that the binary images doesn't have data or bss
diff --git a/arch/arm64/arch.h b/arch/arm64/arch.h
@@ -3,15 +3,6 @@ enum barrier_type {
DSB_SY,
};
-enum sysreg {
- ACTLR_R,
- ID_AA64RMFR0_R,
- RCR_R,
- RDSCR_R,
- SCTLR_R,
- RVBAR_EL3,
-};
-
extern void wsysreg(enum sysreg, unsigned long long v);
extern unsigned long long rsysreg(enum sysreg);
extern void barrier(enum barrier_type type);
diff --git a/arch/arm64/arch.s b/arch/arm64/arch.s
@@ -2,7 +2,6 @@
.text
.globl panic,dohalt,enaint,dopanic
- .globl rsysreg,wsysreg
.globl barrier,vectbl,doswtch,inm8,inm16,inm32
.globl outm8,outm16,outm32
@@ -10,76 +9,6 @@ enaint:
msr daifclr,#15
ret
-/*
- * rsysreg: write a system register
- */
-rsysreg:
- adr x1, 1f
- lsl x0, x0, #3
- add x1, x1, x0
- br x1
-
-1:
-rd_actlr_r:
- mrs x0,S3_6_C1_C0_3
- ret
-
-rd_id_aa64rmfr0_r:
- mrs x0,S3_6_C0_C7_6
- ret
-
-rd_rcr_r:
- mrs x0,S3_6_C1_C1_6
- ret
-
-rd_rdscr_r:
- mrs x0,S3_6_C6_C15_6
- ret
-
-rd_sctlr_r:
- mrs x0,S3_6_C1_C0_6
- ret
-
-rd_rvbar_el3:
- mrs x0,rvbar_el3
- ret
-
-/*
- * wsysreg: write a system register
- */
-wsysreg:
- adr x1, 1f
- lsl x0, x0, #3
- add x1, x1, x0
- br x1
-
-1:
-wr_actlr_r:
- msr S3_6_C1_C0_3,x0
- ret
-
-wr_id_aa64rmfr0_r:
- msr S3_6_C0_C7_6,x0
- ret
-
-wr_rcr_r:
- msr S3_6_C1_C1_6,x0
- ret
-
-wr_rdscr_r:
- msr S3_6_C6_C15_6,x0
- ret
-
-wr_sctlr_r:
- msr S3_6_C1_C0_6,x0
- ret
-
-wr_rvbar_el3:
- b badinst
- ret
-
-
-
barrier:
adr x1, 1f
lsl x0, x0, #3
diff --git a/arch/arm64/gensysreg.sh b/arch/arm64/gensysreg.sh
@@ -0,0 +1,42 @@
+#/bin/sh
+
+set -e
+trap 'r=$?;rm -f $$.tmp;exit $r' EXIT HUP INT QUIT TERM
+
+for i
+do
+ case $i in
+ -h)
+ shift
+ awk 'BEGIN {print "enum sysreg {"}
+ NF == 2 {printf "\t%s,\n", $1}
+ END {print "};"}' $@ > $$.tmp &&
+ mv $$.tmp sysreg.h
+ ;;
+ -s)
+ shift
+ cat <<EOF > $$.tmp && mv $$.tmp sysreg.s
+ .file "sysreg.s"
+
+ .text
+ .globl rsysreg,wsysreg
+rsysreg:
+ adr x1, 1f
+ lsl x0, x0, #3
+ add x1, x1, x0
+ br x1
+1:
+$(awk 'NF == 2 {printf "\tmrs\tx0,%s\n\tret\n\n", $2}' $@)
+
+
+wsysreg:
+ adr x1, 1f
+ lsl x0, x0, #3
+ add x1, x1, x0
+ br x1
+1:
+$(awk 'NF == 2 {printf "\tmsr\t%s,x0\n\tret\n\n", $2}' $@)
+EOF
+ ;;
+ esac
+done
diff --git a/arch/arm64/rom-rmode.c b/arch/arm64/rom-rmode.c
@@ -3,6 +3,7 @@
#include <rcode.h>
#include <uart.h>
+#include "sysreg.h"
#include "arch.h"
void
diff --git a/arch/arm64/sysreg.lst b/arch/arm64/sysreg.lst
@@ -0,0 +1,6 @@
+ACTLR_R S3_6_C1_C0_3
+ID_AA64RMFR0_R S3_6_C0_C7_6
+RCR_R S3_6_C1_C1_6
+RDSCR_R S3_6_C6_C15_6
+SCTLR_R S3_6_C1_C0_6
+RVBAR_EL3 S3_6_C12_C0_1
