commit 5522667ef02b3dd075b3106212bd6e41969a1a5f
parent cea5b60eeaf3e20ecb7803f0e955cff9ad0ba5ae
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date: Fri, 17 Jul 2020 17:22:18 +0200
add arch directory
Change-Id: I055d075e9d3c62bb5ad79d403a5b966d4af09d74
Diffstat:
23 files changed, 899 insertions(+), 0 deletions(-)
diff --git a/src/kernel/arch/Makefile b/src/kernel/arch/Makefile
@@ -0,0 +1,11 @@
+.POSIX:
+PROJECTDIR=../../..
+include $(PROJECTDIR)/scripts/rules.mk
+
+DIRS=hosted native
+
+all:
+ +@cd $(MODE) && $(MAKE)
+
+clean:
+ $(FORALL)
diff --git a/src/kernel/arch/hosted/.gitignore b/src/kernel/arch/hosted/.gitignore
@@ -0,0 +1,2 @@
+romtab.c
+ramtab.c
diff --git a/src/kernel/arch/hosted/9os b/src/kernel/arch/hosted/9os
@@ -0,0 +1,10 @@
+dev
+ root
+ uart
+ dummyuart base=0x1c0c0000,clk=24000000,cfg=b115200 l8 #t0
+ dummyuart base=0x1c0c0100,clk=24000000 #t1
+ cons
+ blk
+ dummyblk
+ ar
+end
diff --git a/src/kernel/arch/hosted/Makefile b/src/kernel/arch/hosted/Makefile
@@ -0,0 +1,27 @@
+.POSIX:
+PROJECTDIR = ../../../..
+include $(PROJECTDIR)/scripts/rules.mk
+
+CRT = $(LIBDIR)/crt.o
+
+ROMOBJS = arch.o \
+ lock.o \
+ kernel.o \
+ $(CRT) \
+ $(SRCDIR)/kernel/builtin.o \
+
+TARGET = $(BINDIR)/kernel.elf
+
+all: $(TARGET) $(BINDIR)/blkfile
+
+$(DIRS): FORCE
+ cd $@ && $(MAKE)
+
+$(BINDIR)/kernel.elf: $(ROMOBJS) $(LIBDEP)
+ $(LD) $(PROJ_LDFLAGS) $(ROMOBJS) $(PROJ_LDLIBS) -o $@
+
+$(BINDIR)/blkfile:
+ dd bs=512 count=2 if=/dev/zero of=$(BINDIR)/blkfile
+
+clean:
+ rm -f $(BINDIR)/blkfile
diff --git a/src/kernel/arch/hosted/arch.c b/src/kernel/arch/hosted/arch.c
@@ -0,0 +1,73 @@
+#include <setjmp.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <9os/9os.h>
+
+#include "hosted.h"
+
+jmp_buf recover;
+
+noreturn void abort(void);
+noreturn void longjmp(jmp_buf env, int val);
+struct trapframe *(*getframe)(void);
+int halted;
+
+void
+dohalt(void)
+{
+ halted = 1;
+ abort();
+}
+
+void
+doswtch(struct trapframe *fp)
+{
+ longjmp(recover, 1);
+}
+
+void
+dopanic(void)
+{
+ struct trapframe *fp;
+
+ fp = (getframe) ? (*getframe)() : NULL;
+ trap(fp);
+ abort();
+}
+
+uint8_t
+inm8(void *addr)
+{
+ return 0;
+}
+
+uint16_t
+inm16(void *addr)
+{
+ return 0;
+}
+
+uint32_t
+inm32(void *addr)
+{
+ return 0;
+}
+
+uint8_t
+outm8(uint8_t val, void *addr)
+{
+ return 0;
+}
+
+uint16_t
+outm16(uint16_t val, void *addr)
+{
+ return 0;
+}
+
+uint32_t
+outm32(uint32_t val, void *addr)
+{
+ return 0;
+}
diff --git a/src/kernel/arch/hosted/hosted.h b/src/kernel/arch/hosted/hosted.h
@@ -0,0 +1,3 @@
+extern jmp_buf recover;
+extern int halted;
+extern struct trapframe *(*getframe)(void);
diff --git a/src/kernel/arch/hosted/kernel.c b/src/kernel/arch/hosted/kernel.c
@@ -0,0 +1,93 @@
+#include <setjmp.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <libk.h>
+#include <9os/9os.h>
+#include <9os/kernel.h>
+
+#include "hosted.h"
+
+static struct trapframe *frame(void);
+
+struct trapframe trapframe, *framep;
+struct trapframe *(*getframe)(void) = frame;
+
+static struct trapframe *
+frame(void)
+{
+ return framep;
+}
+
+void *
+alloc(size_t size)
+{
+ static int lock;
+ void *p;
+
+ if (size == 0) {
+ lock = 1;
+ return NULL;
+ }
+
+ if (lock)
+ panic("alloc");
+
+ if ((p = malloc(size)) == NULL)
+ panic("alloc");
+ return p;
+}
+
+static void
+imach(void)
+{
+ if (setjmp(recover))
+ exit(EXIT_FAILURE);
+ framep = &trapframe;
+}
+
+static void
+namespace(void)
+{
+ int fd;
+ static char setin[] = "addin /dev/uart0/raw\n";
+ static char setout[] = "addout /dev/uart0/raw\n";
+
+ /* Standard input set to 0 */
+ if ((kin = open("#c/raw", O_READ)) < 0)
+ panic("open:#c/raw read");
+
+ /* Standard output set to 1 */
+ if ((kout = open("#c/raw", O_WRITE)) < 0)
+ panic("open:#c/raw write");
+
+ /* Standard error set to 2 */
+ if ((kerr = open("#c/raw", O_WRITE)) < 0)
+ panic("open:#c/raw write");
+
+ if (bind("#t0", "/dev/uart0") < 0)
+ panic("bind:/dev/uart0");
+ if (bind("#c", "/dev/cons") < 0)
+ panic("bind:/dev/cons");
+ if (bind("#b", "/dev/blk") < 0)
+ panic("bind:/dev/blk");
+
+ if ((fd = open("/dev/cons/ctl", O_WRITE)) < 0)
+ panic("open:/dev/cons/ctl write");
+ if (write(fd, setin, sizeof(setin)) < 0)
+ panic("write:setin");
+ if (write(fd, setout, sizeof(setout)) < 0)
+ panic("write:setout");
+ if (close(fd) < 0)
+ panic("close:/dev/cons/ctl");
+}
+
+int
+main(int argc, char *argv[])
+{
+ imach();
+ idev();
+ namespace();
+
+ return debug();
+}
diff --git a/src/kernel/arch/hosted/lock.c b/src/kernel/arch/hosted/lock.c
@@ -0,0 +1 @@
+#include "../lock.c"
diff --git a/src/kernel/arch/lock.c b/src/kernel/arch/lock.c
@@ -0,0 +1,32 @@
+#include <9os/9os.h>
+
+void
+lock(mutex_t *mutex)
+{
+ if (!mutex)
+ panic("lock segfault");
+ if (*mutex)
+ panic("deadlock");
+ *mutex = 1;
+}
+
+void
+unlock(mutex_t *mutex)
+{
+ if (!mutex)
+ panic("unlock segfault");
+ if (!*mutex)
+ panic("unlock");
+ *mutex = 0;
+}
+
+int
+trylock(mutex_t *mutex)
+{
+ if (!mutex)
+ panic("trylock segfault");
+ if (*mutex)
+ return 0;
+ *mutex = 1;
+ return 1;
+}
diff --git a/src/kernel/arch/native/9os b/src/kernel/arch/native/9os
@@ -0,0 +1,11 @@
+dev
+ root
+ uart
+ pl011 base=0x1C090000,clk=24000000,rate=115200
+ pl011 base=0x1c0c0000,clk=24000000,rate=115200
+ cons
+ fip
+ blk
+blob
+ fip.bin 0x8000000,0x80000
+end
diff --git a/src/kernel/arch/native/Makefile b/src/kernel/arch/native/Makefile
@@ -0,0 +1,11 @@
+.POSIX:
+PROJECTDIR=../../../..
+include $(PROJECTDIR)/scripts/rules.mk
+
+DIRS=arm64
+
+all:
+ +@cd $(MODE) && $(MAKE)
+
+clean:
+ $(FORALL)
diff --git a/src/kernel/arch/native/arm64/.gitignore b/src/kernel/arch/native/arm64/.gitignore
@@ -0,0 +1,5 @@
+sysreg.h
+sysreg.s
+version.h
+romtab.c
+ramtab.c
diff --git a/src/kernel/arch/native/arm64/Makefile b/src/kernel/arch/native/arm64/Makefile
@@ -0,0 +1,35 @@
+.POSIX:
+PROJECTDIR = ../../../../..
+include $(PROJECTDIR)/scripts/rules.mk
+
+KERNELOBJS =\
+ kernel-crt.o \
+ kernel.o \
+ arch.o \
+ debug_lock.o \
+ sysreg.o \
+ $(SRCDIR)/romfw/builtin.o \
+ cache.o \
+
+TARGET = $(BINDIR)/kernel.bin
+
+all: $(TARGET)
+
+kernel.o.o: sysreg.h version.h
+cache.o: sysreg.h
+
+sysreg.h: sysreg.lst
+ mksysreg -h sysreg.lst
+
+sysreg.s: sysreg.lst
+ mksysreg -s sysreg.lst
+
+version.h:
+ mkver
+
+$(BINDIR)/romfw.elf: $(ROMOBJS) $(LIBDEP)
+ $(LD) $(PROJ_LDFLAGS) $(LINKSCRIPT) $(ROMOBJS) $(PROJ_LDLIBS) -o $@
+
+clean:
+ rm -f $(TARGET:.bin=.elf)
+ rm -f sysreg.h sysreg.s version.h
diff --git a/src/kernel/arch/native/arm64/arch.h b/src/kernel/arch/native/arm64/arch.h
@@ -0,0 +1,11 @@
+enum barrier_type {
+ ISB,
+ DSB_SY,
+};
+
+extern void wsysreg(enum sysreg, unsigned long long v);
+extern unsigned long long rsysreg(enum sysreg);
+extern void barrier(enum barrier_type type);
+extern void invdcachesetway(void *addr);
+extern void invdcache(void);
+extern void invicache(void);
diff --git a/src/kernel/arch/native/arm64/arch.s b/src/kernel/arch/native/arm64/arch.s
@@ -0,0 +1,195 @@
+ .file "arch.s"
+
+ .text
+ .globl panic,dohalt,intr,dopanic
+ .globl barrier,vectbl,doswtch,inm8,inm16,inm32
+ .globl outm8,outm16,outm32
+ .globl invdcachesetway,invicache,vectbl,doswtch
+ .globl inm8,inm16,inm32,outm8,outm16,outm32
+
+intr:
+ cmp x0,#0
+ b.ne 1f
+ msr daifset,#15
+ ret
+1:
+ msr daifclr,#15
+ ret
+
+barrier:
+ adr x1, 1f
+ lsl x0, x0, #3
+ add x1, x1, x0
+ br x1
+
+1:
+ isb
+ ret
+ dsb sy
+ ret
+
+invdcachesetway:
+ dc isw,x0
+ ret
+
+invicache:
+ ic iallu
+ ret
+
+badinst:
+ adr x0,badimsg
+ b panic
+
+ .section .rodata
+badimsg:
+ .asciz "invalid instruction"
+
+ .text
+inm8:
+ ldrb w0,[x0]
+ ret
+
+inm16:
+ ldrh w0,[x0]
+ ret
+
+inm32:
+ ldr w0,[x0]
+ ret
+
+outm8:
+ strb w0,[x1]
+ ret
+
+outm16:
+ strh w0,[x1]
+ ret
+
+outm32:
+ str w0,[x1]
+ ret
+
+dohalt:
+ msr daifset,#15
+ wfe
+ b dohalt
+
+dopanic:
+exception:
+ msr spsel,#1
+ stp x0,x1,[sp,#-16*(19-0)]
+ stp x2,x3,[sp,#-16*(19-1)]
+ stp x4,x5,[sp,#-16*(19-2)]
+ stp x6,x7,[sp,#-16*(19-3)]
+ stp x8,x9,[sp,#-16*(19-4)]
+ stp x10,x11,[sp,#-16*(19-5)]
+ stp x12,x13,[sp,#-16*(19-6)]
+ stp x14,x15,[sp,#-16*(19-7)]
+ stp x16,x17,[sp,#-16*(19-8)]
+ stp x18,x19,[sp,#-16*(19-9)]
+ stp x20,x21,[sp,#-16*(19-10)]
+ stp x22,x23,[sp,#-16*(19-11)]
+ stp x24,x25,[sp,#-16*(19-12)]
+ stp x26,x27,[sp,#-16*(19-13)]
+ stp x28,x29,[sp,#-16*(19-14)]
+
+ mrs x9,ELR_EL3
+ stp x9,x30,[sp,#-16*(19-15)]
+
+ mrs x9,SPSR_EL3
+ mrs x10,ESR_EL3
+ stp x9,x10,[sp,#-16*(19-16)]
+
+ mov x9,sp
+ mrs x10,FAR_EL3
+ stp x9,x10,[sp,#-16*(19-17)]
+
+ mrs x9,scr_el3
+ mov x10,#0 /* unused */
+ stp x9,x10,[sp,#-16*(19-18)]
+
+ sub sp,sp,#16*19
+ mov x0,sp
+ mov x29,#0
+ bl trap
+ adr x0,outsync
+ b panic
+
+ .section .rodata
+outsync:
+ .asciz "out of sync"
+
+ .text
+doswtch:
+ ldp x9,x10,[x0,#16*18]
+ msr SCR_EL3,x9
+
+ ldp x9,x10,[x0,#16*17]
+ msr FAR_EL3,x10
+ mov sp,x9
+
+ ldp x9,x10,[x0,#16*16]
+ msr ESR_EL3,x10
+ msr SPSR_EL3,x9
+
+ ldp x9,x30,[x0,#16*15]
+ msr ELR_EL3,x9
+
+ ldp x28,x29,[x0,#16*14]
+ ldp x26,x27,[x0,#16*13]
+ ldp x24,x25,[x0,#16*12]
+ ldp x22,x23,[x0,#16*11]
+ ldp x20,x21,[x0,#16*10]
+ ldp x18,x19,[x0,#16*9]
+ ldp x16,x17,[x0,#16*8]
+ ldp x14,x15,[x0,#16*7]
+ ldp x12,x13,[x0,#16*6]
+ ldp x10,x11,[x0,#16*5]
+ ldp x8,x9,[x0,#16*4]
+ ldp x6,x7,[x0,#16*3]
+ ldp x4,x5,[x0,#16*2]
+ ldp x2,x3,[x0,#16*1]
+ ldp x0,x1,[x0,#16*0]
+
+ eret
+
+ .align 11
+vectbl:
+ /* Current EL with SP0 */
+ b exception /* Sync */
+ .align 7
+ b exception /* IRQ/vIRQ */
+ .align 7
+ b exception /* FIQ/vFIQ */
+ .align 7
+ b exception /* SError/VSError */
+
+ /* Current EL with SPx */
+ .align 7
+ b exception /* Sync */
+ .align 7
+ b exception /* IRQ/vIRQ */
+ .align 7
+ b exception /* FIQ/vFIQ */
+ .align 7
+ b exception /* SError/VSError */
+
+ /* Lower EL using AArch64 */
+ .align 7
+ b exception /* Sync */
+ .align 7
+ b exception /* IRQ/vIRQ */
+ .align 7
+ b exception /* FIQ/vFIQ */
+ .align 7
+ b exception /* SError/VSError */
+
+ /* Lower EL using AArch32 */
+ .align 7
+ b exception /* Sync */
+ .align 7
+ b exception /* IRQ/vIRQ */
+ .align 7
+ b exception /* FIQ/vFIQ */
+ .align 7
+ b exception /* SError/VSError */
diff --git a/src/kernel/arch/native/arm64/cache.c b/src/kernel/arch/native/arm64/cache.c
@@ -0,0 +1,88 @@
+#include <9os/9os.h>
+
+#include "sysreg.h"
+#include "arch.h"
+
+#define NR_LEVELS 7
+
+/* clidr_el1 */
+#define LOC_SHIFT 24
+#define LOC_MASK 0x7 /* level of coherence */
+#define CTYPE_MASK 0x7 /* cache type */
+
+/* ccsidr_el1 */
+#define NSETS_SHIFT 13
+#define NSETS_MASK 0x7fff /* (number of sets in cache) - 1 */
+#define NWAYS_SHIFT 3
+#define NWAYS_MASK 0x3ff /* (associativty of cache) - 1 */
+#define LINE_MASK 0x7 /* log2(cache line in bytes) - 4 */
+
+/* csselr_el1 */
+#define LEVEL_SHIFT 1 /* cache level required */
+
+static unsigned
+log2(unsigned long long v, unsigned width)
+{
+ unsigned nbits, i = width;
+
+ for (nbits = 0; i-- > 0; nbits++) {
+ if ((v & (1ull << i)) != 0)
+ break;
+ }
+ return width - nbits - 1;
+}
+
+static void
+invdcachelvl(unsigned l)
+{
+ unsigned long long ccsidr;
+ unsigned nsets, nways, size, shift, i, j;
+
+ wsysreg(CSSELR_EL1, l << LEVEL_SHIFT);
+ barrier(ISB);
+
+ ccsidr = rsysreg(CCSIDR_EL1);
+ nsets = ((ccsidr >> NSETS_SHIFT) & NSETS_MASK) + 1;
+ nways = ((ccsidr >> NWAYS_SHIFT) & NWAYS_MASK) + 1;
+ size = (ccsidr & LINE_MASK) + 4;
+ shift = 32 - log2(nways, 32);
+
+ for (i = 0; i < nways; i++) {
+ for (j = 0; j < nsets; j++) {
+ uintptr_t addr;
+
+ addr = (uintptr_t)i << shift | j << size | l << 1;
+ invdcachesetway((void *)addr);
+ }
+ }
+ barrier(DSB_SY);
+}
+
+void
+invdcache(void)
+{
+ unsigned long long clidr;
+ unsigned l;
+ enum cachetype {
+ NOCACHE,
+ ICACHE,
+ DCACHE,
+ HARVARD,
+ UNIFIED
+ } type;
+
+ barrier(DSB_SY);
+
+ clidr = rsysreg(CLIDR_EL1);
+ if (((clidr >> LOC_SHIFT) & LOC_MASK) == 0)
+ return;
+
+ for (l = 0; l < NR_LEVELS; l++) {
+ type = clidr & CTYPE_MASK;
+ if (type == NOCACHE || type == ICACHE)
+ continue;
+
+ invdcachelvl(l);
+ clidr >>= 3;
+ }
+}
diff --git a/src/kernel/arch/native/arm64/crt-kernel.s b/src/kernel/arch/native/arm64/crt-kernel.s
@@ -0,0 +1,45 @@
+
+ .file "crt.s"
+ .text
+ .globl _start
+
+_start:
+ adr x0,vectbl
+ msr VBAR_EL3,x0
+ isb
+
+ /* Differentiate between cold and warm boot (FVP only) */
+ mrs x2, mpidr_el1
+ ldr x1,=0x1c100000
+ str w2, [x1, 0x10]
+ ldr w2, [x1, 0x10]
+ ubfx w2, w2, 24, 2
+ cmp w2, 2
+ beq warm
+ cmp w2, 3
+ beq warm
+
+ ldr x0,=end /* Setup an initial stack */
+ mov x1,#0x100f /* 1 page + 15 */
+ add x0,x0,x1
+ bic x0,x0,#0xf /* Align to 16 bytes */
+ mov sp,x0
+
+ ldr x0,=edata /* BSS clean */
+ mov x1,#0
+ ldr x2,=end
+ sub x2,x2,x0
+ bl memset
+
+ bl main
+ adr x0,outsync
+ b panic
+
+warm:
+ /* Hardcoded address of BL2 at EL3 */
+ ldr x0,=0x4022000
+ br x0
+
+ .section .rodata
+outsync:
+ .asciz "out of sync"
diff --git a/src/kernel/arch/native/arm64/debug_lock.c b/src/kernel/arch/native/arm64/debug_lock.c
@@ -0,0 +1 @@
+#include "../../lock.c"
diff --git a/src/kernel/arch/native/arm64/kernel.c b/src/kernel/arch/native/arm64/kernel.c
@@ -0,0 +1,160 @@
+#include <errno.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <libk.h>
+#include <limits.h>
+#include <9os/9os.h>
+#include <9os/kernel.h>
+
+#include "version.h"
+#include "sysreg.h"
+#include "arch.h"
+
+#define ENVSIZ 512
+#define STACKSIZ 1792
+#define HEAPSIZ 1792
+
+/* TODO: Move these constants to a autogenerated file */
+#define BL2BASE ((void *) 0x4022000)
+#define BL33BASE ((void *) 0x88000000)
+#define DTBBASE ((void *) 0x82000000)
+
+
+typedef struct mach Mach;
+
+char **_environ;
+struct trapframe trapframe, *framep;
+
+struct mach {
+ void *sp;
+ size_t stacksiz;
+ void *env;
+ size_t envsiz;
+};
+
+void *
+alloc(size_t size)
+{
+ static char heap[HEAPSIZ];
+ static char *base = heap;
+ static int lock;
+ char *bp;
+
+ if (size == 0) {
+ lock = 1;
+ return NULL;
+ }
+
+ if (lock)
+ panic("alloc");
+
+ bp = base;
+ if (&bp[size] > &heap[HEAPSIZ])
+ return NULL;
+ base += size;
+ return bp;
+}
+
+static void
+imach(Mach *mp, void *stackp)
+{
+ framep = &trapframe;
+ memset(framep, 0, sizeof(*framep));
+
+ mp->sp = stackp;
+ mp->stacksiz = STACKSIZ;
+ mp->env = stackp + ENVSIZ;
+ mp->envsiz = ENVSIZ;
+
+ _environ = mp->env;
+
+ framep->r[SP] = (unsigned long long)mp->sp;
+ framep->r[ELR] = 0x4022000;
+ framep->r[SPSR] = 0xf << 6 | 0xd;
+
+ rmctab = &romtab;
+
+ invicache();
+ invdcache();
+}
+
+static void
+info(Mach *mp)
+{
+ dbg(kout,
+ "romfw: version %s\n"
+ "env = %p, envsiz = 0x%zx\n"
+ "sp = %p, stacksiz = 0x%zx\n",
+ RCODEVERSION,
+ mp->env, mp->envsiz,
+ mp->sp, mp->stacksiz);
+}
+
+static void
+namespace(void)
+{
+ int fd;
+ static char setin[] = "addin /dev/uart0/raw\n";
+ static char setout[] = "addout /dev/uart0/raw\n";
+
+ /* Standard input set to 0 */
+ if ((kin = open("#c/raw", O_READ)) < 0)
+ panic("open:#c/raw read");
+
+ /* Standard output set to 1 */
+ if ((kout = open("#c/raw", O_WRITE)) < 0)
+ panic("open:#c/raw write");
+
+ /* Standard error set to 2 */
+ if ((kerr = open("#c/raw", O_WRITE)) < 0)
+ panic("open:#c/raw write");
+
+ if (bind("#c", "/dev/cons") < 0) {
+ panic("bind:/dev/cons");
+ if (bind("#t0", "/dev/uart0") < 0) {
+ panic("bind:/dev/uart0");
+ if (bind("#t1", "/dev/uart3") < 0) {
+ panic("bind:/dev/uart3");
+
+ if ((fd = open("/dev/cons/ctl", O_WRITE)) < 0) {
+ panic("open:/dev/cons/ctl write");
+ if (write(fd, setin, sizeof(setin)) < 0) {
+ panic("write:setin");
+ if (write(fd, setout, sizeof(setout)) < 0) {
+ panic("write:setout");
+ if (close(fd) < 0) {
+ panic("close:/dev/cons/ctl");
+
+ if (mount("#F", "/fip", "/blobs/fip.bin") < 0) {
+ panic("mount:/fip");
+
+ return;
+}
+
+void
+loadfip(void)
+{
+ if (loadimg("/fip/bl2.bin", BL2BASE, NULL) < 0)
+ panic("bl2 missing");
+ if (loadimg("/fip/bl33.bin", BL33BASE, NULL) < 0)
+ panic("bl33 missing");
+ if (loadimg("/fip/hw.cfg", DTBBASE, NULL) < 0)
+ panic("dtb missing");
+}
+
+void
+main(void *stackp)
+{
+ Mach mach;
+
+ imach(&mach, stackp);
+ idev();
+ intr(IENABLE);
+ barrier(ISB);
+ namespace();
+ info(&mach);
+ debug();
+ loadfip();
+ swtch(framep);
+}
diff --git a/src/kernel/arch/native/arm64/lock.s b/src/kernel/arch/native/arm64/lock.s
@@ -0,0 +1,26 @@
+.globl lock,unlock,trylock
+
+/*
+ * Those functions are currently not used for two reasons:
+ * 1- We don't have caches and mmu enabled
+ * 2- We are executing only one execution thread.
+ */
+
+lock:
+ mov w2,#1
+ sevl
+1:
+ wfe
+ mov w1,wzr
+ casa w1,w2,[x0]
+ cbnz w1,1b
+ ret
+
+unlock:
+ stlr wzr,[x0]
+ sev
+ ret
+
+trylock: // TODO: implement trylock
+ mov w0,#1
+ ret
diff --git a/src/kernel/arch/native/arm64/mksysreg b/src/kernel/arch/native/arm64/mksysreg
@@ -0,0 +1,42 @@
+#/bin/sh
+
+set -e
+trap 'r=$?;rm -f $$.tmp;exit $r' EXIT HUP INT QUIT TERM
+
+for i
+do
+ case $i in
+ -h)
+ shift
+ awk 'BEGIN {print "enum sysreg {"}
+ NF == 2 {printf "\t%s,\n", $1}
+ END {print "};"}' $@ > $$.tmp &&
+ mv $$.tmp sysreg.h
+ ;;
+ -s)
+ shift
+ cat <<EOF > $$.tmp && mv $$.tmp sysreg.s
+ .file "sysreg.s"
+
+ .text
+ .globl rsysreg,wsysreg
+rsysreg:
+ adr x1,1f
+ lsl x0,x0,#3
+ add x1,x1,x0
+ br x1
+1:
+$(awk 'NF == 2 {printf "\tmrs\tx0,%s\n\tret\n\n", $2}' $@)
+
+
+wsysreg:
+ adr x2,1f
+ lsl x0,x0,#3
+ add x2,x2,x0
+ br x2
+1:
+$(awk 'NF == 2 {printf "\tmsr\t%s,x1\n\tret\n\n", $2}' $@)
+EOF
+ ;;
+ esac
+done
diff --git a/src/kernel/arch/native/arm64/mkver b/src/kernel/arch/native/arm64/mkver
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+set -e
+trap 'r=$?;rm -f $$.tmp;exit $r' EXIT HUP INT QUIT TERM
+
+git show-ref HEAD |
+awk '{printf("#define RCODEVERSION \"%s\"\n",
+ substr($1, 1, 8))
+}' > $$.tmp && mv $$.tmp version.h
diff --git a/src/kernel/arch/native/arm64/sysreg.lst b/src/kernel/arch/native/arm64/sysreg.lst
@@ -0,0 +1,8 @@
+ACTLR_EL3 S3_6_C1_C0_1
+SCTLR_EL3 S3_6_C1_C0_0
+RVBAR_EL3 S3_6_C12_C0_1
+VBAR_EL3 S3_6_C12_C0_0
+TPIDR_EL3 S3_6_C13_C0_2
+CLIDR_EL1 S3_1_C0_C0_1
+CCSIDR_EL1 S3_1_C0_C0_0
+CSSELR_EL1 S3_2_C0_C0_0
