commit 5360a03924e8be5e9b17ec750fa442fc93eb0161
parent 4c21257b1984c358159853bf4ae683cae0b96404
Author: Roberto Vargas <roberto.vargas@arm.com>
Date: Tue, 9 Oct 2018 17:17:37 +0100
Add the json files to the repository
Diffstat:
30 files changed, 1481 insertions(+), 0 deletions(-)
diff --git a/json/RMSA.json b/json/RMSA.json
@@ -0,0 +1,14 @@
+{
+ "_type": "RMSA.RMSA",
+ "register_blocks": [
+ { "_include": "registers/RSCB.json" }
+ ],
+ "registers": [
+ { "_include": "registers/RSCB_RLE.json" }
+ ],
+ "structures": [
+ { "_include": "structures/CRGTE.json" },
+ { "_include": "structures/L0RGTE.json" },
+ { "_include": "structures/RGTE.json" }
+ ]
+}
+\ No newline at end of file
diff --git a/json/enums/RPG_GlobalAccessPermissions.json b/json/enums/RPG_GlobalAccessPermissions.json
@@ -0,0 +1,6 @@
+{
+ "0b000": "nRnWnX",
+ "0b001": "RnWnX",
+ "0b010": "nRWnX",
+ "0b011": "RWnX"
+}
diff --git a/json/enums/RPG_OwnerAccessPermissions.json b/json/enums/RPG_OwnerAccessPermissions.json
@@ -0,0 +1,10 @@
+{
+ "0b000": "nRnWnX",
+ "0b001": "RnWnX",
+ "0b010": "nRWnX",
+ "0b011": "RWnX",
+ "0b100": "nRnWX",
+ "0b101": "RnWX",
+ "0b110": "nRWX",
+ "0b111": "RWX"
+}
diff --git a/json/enums/RPG_State.json b/json/enums/RPG_State.json
@@ -0,0 +1,13 @@
+{
+ "0b0000": "Invalid",
+ "0b0001": "Valid",
+ "0b0010": "Reserved",
+ "0b0011": "RD",
+ "0b0100": "REC",
+ "0b0101": "MDT",
+ "0b0110": "AddDestination",
+ "0b0111": "ExportSource",
+ "0b1000": "ExportDestination",
+ "0b1001": "ImportDestination",
+ "0b1010": "RealmAttestationReport"
+}
diff --git a/json/registers/RSCB.json b/json/registers/RSCB.json
@@ -0,0 +1,31 @@
+{
+ "_type": "RegisterBlock",
+ "name": "RSCB",
+ "title": "Realm System Configuration Block (RSCB)",
+ "registers": [
+ { "_include": "RSCB_CTRL.json" },
+ { "_include": "RSCB_RPU_CFG.json" },
+ { "_include": "RSCB_L0RGT_HDR.json" },
+ { "_include": "RSCB_GLOBAL_LOCK.json" },
+ { "_include": "RSCB_HW_VER.json" },
+ { "_include": "RSCB_ROM_VER.json" },
+ { "_include": "RSCB_RAM_VER.json" },
+ { "_include": "RSCB_SYS_PROPS.json" },
+ { "_include": "RSCB_GP0.json" },
+ { "_include": "RSCB_GP1.json" },
+ { "_include": "RSCB_GP2.json" },
+ { "_include": "RSCB_GP3.json" },
+ { "_include": "RSCB_NONCE.json" },
+ { "_include": "RSCB_STATE.json" },
+ { "_include": "RSCB_EVENT_VEC.json" },
+ { "_include": "RSCB_EVENT_CTX.json" }
+ ],
+ "size": 1024,
+ "default_access": {
+ "_type": "Accessors.Permission.Access",
+ "access": {
+ "_type": "Accessors.Permission.AccessTypes.RAZWI"
+ },
+ "condition": "TRUE"
+ }
+}
+\ No newline at end of file
diff --git a/json/registers/RSCB_CTRL.json b/json/registers/RSCB_CTRL.json
@@ -0,0 +1,114 @@
+{
+ "_type": "Register",
+ "name": "RSCB_CTRL",
+ "title": "RSCB Control",
+ "purpose": "Top-level controls for RCSB.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x0",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 64,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "0",
+ "name": "EN",
+ "description": "System Realm Enablement Status.",
+ "values": {
+ "0b0": "Disabled",
+ "0b1": "Enabled"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "1",
+ "name": "PREG_LOCK",
+ "description": "Protected Registers Lock.",
+ "values": {
+ "0b0": "Unlocked",
+ "0b1": "Locked"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "2",
+ "name": "DBG",
+ "description": "Debug.",
+ "values": {
+ "0b0": "Disabled",
+ "0b1": "Enabled"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "5",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "4",
+ "name": "RMU_WLOCK",
+ "description": "RMU Write Lock.",
+ "values": {
+ "0b0": "Unlocked",
+ "0b1": "Locked"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "3",
+ "name": "ROT_WLOCK",
+ "description": "ROT Write Lock.",
+ "values": {
+ "0b0": "Unlocked",
+ "0b1": "Locked"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "6",
+ "name": "RSCB_LOCK",
+ "description": [
+ "RSCB Lock.",
+ "If this bit is set, all RSCB registers become write protected until the next system reset event."
+ ],
+ "values": {
+ "0b0": "Disabled",
+ "0b1": "Enabled"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "7",
+ "name": "ALIVE",
+ "description": "RSCB Alive.",
+ "values": {
+ "0b0": "Dead",
+ "0b1": "Alive"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "63:8",
+ "value": "RES0"
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_EVENT_CTX.json b/json/registers/RSCB_EVENT_CTX.json
@@ -0,0 +1,58 @@
+{
+ "_type": "Register",
+ "name": "RSCB_EVENT_CTX",
+ "title": "RSCB Event Context",
+ "purpose": "Event context for RCSB.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x300",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 64,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "5:0",
+ "name": "INDEX",
+ "description": "Latched event index."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "11:6",
+ "name": "CLIENT",
+ "description": [
+ "Client ID.",
+ "For example, RPU Index or MPE Index."
+ ]
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "51:12",
+ "name": "ADDR",
+ "description": "Memory address."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "55:52",
+ "name": "SUBTYPE",
+ "description": "Event subtype."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_EVENT_VEC.json b/json/registers/RSCB_EVENT_VEC.json
@@ -0,0 +1,95 @@
+{
+ "_type": "Register",
+ "name": "RSCB_EVENT_VEC",
+ "title": "RSCB Event Vector",
+ "purpose": "Event vector for RCSB.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x2E0",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "0",
+ "name": "FATAL",
+ "description": [
+ "System fatal error.",
+ "Set by trusted System Controller when an error that risks Bowmore integrity is encountered."
+ ],
+ "values": {
+ "0b0": "No error",
+ "0b1": "Error"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "1",
+ "name": "SRAM_RAS",
+ "description": "RMU SRAM RAS error",
+ "values": {
+ "0b0": "No error",
+ "0b1": "Error"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "2",
+ "name": "PREG_WB",
+ "description": "Protected register write blocked",
+ "values": {
+ "0b0": "Not blocked",
+ "0b1": "Blocked"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "3",
+ "name": "RPU_ERR",
+ "description": [
+ "RPU error",
+ "Set when any RPU encounters an error or an abort"
+ ],
+ "values": {
+ "0b0": "No error",
+ "0b1": "Error"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "4",
+ "name": "MPE_ERR",
+ "description": [
+ "MPE error",
+ "Set when any MPE encounters an uncorrectable RAS error"
+ ],
+ "values": {
+ "0b0": "No error",
+ "0b1": "Error"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "31:5",
+ "value": "RES0"
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_GLOBAL_LOCK.json b/json/registers/RSCB_GLOBAL_LOCK.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_GLOBAL_LOCK",
+ "title": "RSCB Global Lock",
+ "purpose": "Synchronizing RMU access to global RMU resources.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x140",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 64,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "63:0",
+ "name": "LOCK",
+ "description": "Global lock."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_GP0.json b/json/registers/RSCB_GP0.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_GP0",
+ "title": "RSCB General Purpose Register 0",
+ "purpose": "RSCB General Purpose Register.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x200",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:0",
+ "name": "REG",
+ "description": "General purpose register."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_GP1.json b/json/registers/RSCB_GP1.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_GP1",
+ "title": "RSCB General Purpose Register 1",
+ "purpose": "RSCB General Purpose Register.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x220",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:0",
+ "name": "REG",
+ "description": "General purpose register."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_GP2.json b/json/registers/RSCB_GP2.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_GP2",
+ "title": "RSCB General Purpose Register 2",
+ "purpose": "RSCB General Purpose Register.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x240",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:0",
+ "name": "REG",
+ "description": "General purpose register."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_GP3.json b/json/registers/RSCB_GP3.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_GP3",
+ "title": "RSCB General Purpose Register 3",
+ "purpose": "RSCB General Purpose Register.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x260",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:0",
+ "name": "REG",
+ "description": "General purpose register."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_HW_VER.json b/json/registers/RSCB_HW_VER.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_HW_VER",
+ "title": "RSCB Hardware Version",
+ "purpose": "Version of RSCB hardware.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x180",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:0",
+ "name": "VERSION",
+ "description": "Version."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_L0RGT_HDR.json b/json/registers/RSCB_L0RGT_HDR.json
@@ -0,0 +1,110 @@
+{
+ "_type": "Register",
+ "name": "RSCB_L0RGT_HDR",
+ "title": "RSCB L0RGT Header",
+ "purpose": "Top-level configuration of the RGT.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x80",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 64,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "0",
+ "name": "VALID",
+ "description": "Valid.",
+ "values": {
+ "0b0": "Invalid",
+ "0b1": "Valid"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "5:1",
+ "name": "ENTRIES",
+ "description": [
+ "Exponent of number of L0RGT entries.",
+ "`NumEntries = 2^RSCB_L0RGT_HDR.ENTRIES`"
+ ]
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "11:6",
+ "name": "SEGSIZE",
+ "description": [
+ "Exponent of L0RGT global segment size.",
+ "`GlobalSegmentSize = 2^RSCB_L0RGT_HDR.SEGSIZE`"
+ ]
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "51:12",
+ "name": "BADDR",
+ "description": "Base address in RM1 space, specified in 4KB granularity."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "55:52",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "57:56",
+ "name": "IRGN",
+ "description": "Inner cacheability attributes.",
+ "values": {
+ "0b00": "Normal memory, Inner Non-cacheable.",
+ "0b01": "Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable.",
+ "0b10": "Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable.",
+ "0b11": "Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable."
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "59:58",
+ "name": "ORGN",
+ "description": "Outer cacheability attributes.",
+ "values": {
+ "0b00": "Normal memory, Outer Non-cacheable.",
+ "0b01": "Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable.",
+ "0b10": "Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable.",
+ "0b11": "Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable."
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "61:60",
+ "name": "SH",
+ "description": "Shareability attributes.",
+ "values": {
+ "0b00": "Non-shareable",
+ "0b10": "Outer Shareable",
+ "0b11": "Inner Shareable"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "63:62",
+ "value": "RES0"
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_NONCE.json b/json/registers/RSCB_NONCE.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_NONCE",
+ "title": "RSCB Nonce",
+ "purpose": "RSCB Nonce.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x280",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 64,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "64:0",
+ "name": "NONCE",
+ "description": "Nonce counter."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_RAM_VER.json b/json/registers/RSCB_RAM_VER.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_RAM_VER",
+ "title": "RSCB RAM Version",
+ "purpose": "Version of RSCB RAM.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x1C0",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:0",
+ "name": "MIN_VERSION",
+ "description": "Minimum version."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_RLE.json b/json/registers/RSCB_RLE.json
@@ -0,0 +1,70 @@
+{
+ "_type": "Register",
+ "name": "RSCB_RLE",
+ "title": "RSCB Resource List Entry",
+ "purpose": "Resource List Entry.",
+ "state": "AArch64",
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 64,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "3:0",
+ "name": "TYPE",
+ "description": [
+ "Type of the entry.",
+ "The value of this field determines the format of the VALUE field."
+ ],
+ "values": [
+ {
+ "_type": "Values.Value",
+ "value": "0b000",
+ "meaning": "Invalid"
+ },
+ {
+ "_type": "Values.Link",
+ "value": "0b001",
+ "meaning": "MPE",
+ "links": {
+ "VALUE": "Mapped"
+ }
+ },
+ {
+ "_type": "Values.Link",
+ "value": "0b010",
+ "meaning": "RM1 SRAM",
+ "links": {
+ "VALUE": "RM1_SRAM"
+ }
+ },
+ {
+ "_type": "Values.Link",
+ "value": "0b011",
+ "meaning": "Realm DRAM",
+ "links": {
+ "VALUE": "REALM_DRAM"
+ }
+ }
+ ]
+ },
+ {
+ "_type": "Fields.Dynamic",
+ "rangeset": "63:4",
+ "name": "VALUE",
+ "description": [
+ "Value of the entry",
+ "The format of this field is determined by the value of the TYPE field."
+ ],
+ "instances": [
+ { "_include": "RSCB_RLE_INVALID.json" },
+ { "_include": "RSCB_RLE_MPE.json" },
+ { "_include": "RSCB_RLE_RM1_SRAM.json" },
+ { "_include": "RSCB_RLE_REALM_DRAM.json" }
+ ]
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_RLE_INVALID.json b/json/registers/RSCB_RLE_INVALID.json
@@ -0,0 +1,17 @@
+{
+ "_type": "Fieldset",
+ "name": "Invalid",
+ "width": 61,
+ "values": [
+ {
+ "_type": "Fields.ConstantField",
+ "rangeset": "60:0",
+ "name": "ZERO",
+ "value": {
+ "_type": "Values.Value",
+ "meaning": "This field is zero",
+ "value": "0x0"
+ }
+ }
+ ]
+}
diff --git a/json/registers/RSCB_RLE_MPE.json b/json/registers/RSCB_RLE_MPE.json
@@ -0,0 +1,23 @@
+{
+ "_type": "Fieldset",
+ "name": "MPE",
+ "width": 61,
+ "values": [
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "9:0",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "49:10",
+ "name": "BADDR",
+ "description": "Base address in RM1 space, specified in 4KB granularity."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "60:50",
+ "value": "RES0"
+ }
+ ]
+}
diff --git a/json/registers/RSCB_RLE_REALM_DRAM.json b/json/registers/RSCB_RLE_REALM_DRAM.json
@@ -0,0 +1,46 @@
+{
+ "_type": "Fieldset",
+ "name": "Realm DRAM",
+ "width": 61,
+ "values": [
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "9:0",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "49:10",
+ "name": "BADDR",
+ "description": "Realm DRAM base address in RM1 space, specified in 4KB granularity."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "55:50",
+ "name": "SIZE",
+ "description": [
+ "Exponent of Realm DRAM region size.",
+ "`RealmDramRegionSize = 2^RSCB_RLE_REALM_DRAM.SIZE`"
+ ]
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "59:56",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "60",
+ "name": "LIVE",
+ "description": [
+ "Realm DRAM live.",
+ "This flag is set by the System Integrator for physical address spaces that are guaranteed to contain functional DRAM.",
+ "The RMU is allowed to place RGT tables only in physical address ranges that are mapped to a Live DRAM."
+ ],
+ "values": {
+ "0b0": "Not functional",
+ "0b1": "Functional"
+ }
+ }
+ ]
+}
diff --git a/json/registers/RSCB_RLE_RM1_SRAM.json b/json/registers/RSCB_RLE_RM1_SRAM.json
@@ -0,0 +1,42 @@
+{
+ "_type": "Fieldset",
+ "name": "RM1 SRAM",
+ "width": 61,
+ "values": [
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "4:0",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "8:5",
+ "name": "SIZE_LSB",
+ "description": "SRAM region size LSB, specified in 4KB granularity."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "48:9",
+ "name": "BADDR",
+ "description": "SRAM base address in RM1 space, specified in 4KB granularity."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "58:49",
+ "name": "SIZE_MSB",
+ "description": "SRAM region size MSB, specified in 4KB granularity."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "60:59",
+ "name": "HIERARCHY",
+ "description": "SRAM hierarchy.",
+ "values": {
+ "0b00": "Global",
+ "0b01": "PE cluster",
+ "0b10": "PE",
+ "0b11": "Reserved"
+ }
+ }
+ ]
+}
diff --git a/json/registers/RSCB_ROM_VER.json b/json/registers/RSCB_ROM_VER.json
@@ -0,0 +1,37 @@
+{
+ "_type": "Register",
+ "name": "RSCB_ROM_VER",
+ "title": "RSCB ROM Version",
+ "purpose": "Version of RSCB ROM.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x1A0",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:0",
+ "name": "VERSION",
+ "description": "Version."
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_RPU_CFG.json b/json/registers/RSCB_RPU_CFG.json
@@ -0,0 +1,71 @@
+{
+ "_type": "Register",
+ "name": "RSCB_RPU_CFG",
+ "title": "RPU Configuration",
+ "purpose": "Top-level RPU configuration.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x40",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "1:0",
+ "name": "RPGSIZE",
+ "description": "Realm Protection Granule Size.",
+ "values": {
+ "0b00": "4KB",
+ "0b01": "16KB",
+ "0b10": "64KB",
+ "0b11": "Reserved"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "7:2",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "9:8",
+ "name": "SPEC",
+ "description": "Speculation control."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "15:10",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "23:16",
+ "name": "SRPUPRIV",
+ "description": "SRPU private configuration."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "31:24",
+ "name": "PEPRIV",
+ "description": "PE RPU private configuration."
+ }
+ ]
+ }
+ ]
+}
+\ No newline at end of file
diff --git a/json/registers/RSCB_STATE.json b/json/registers/RSCB_STATE.json
@@ -0,0 +1,42 @@
+{
+ "_type": "Register",
+ "name": "RSCB_STATE",
+ "title": "RSCB State",
+ "purpose": "RSCB state.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x2C0",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "7:0",
+ "name": "EXTDBG",
+ "description": "External debug state."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "31:8",
+ "value": "RES0"
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/registers/RSCB_SYS_PROPS.json b/json/registers/RSCB_SYS_PROPS.json
@@ -0,0 +1,105 @@
+{
+ "_type": "Register",
+ "name": "RSCB_SYS_PROPS",
+ "title": "RSCB System Properties",
+ "purpose": "RSCB System Properties.",
+ "state": "AArch64",
+ "accessors": [
+ {
+ "_type": "Accessors.MemoryMapped",
+ "component": "RSCB",
+ "offset": "0x1E0",
+ "permissionset": [
+ {
+ "_type": "Accessors.Permission.Access",
+ "access": "RW",
+ "condition": null
+ }
+ ],
+ "power_domain": "Unknown",
+ "range": null
+ }
+ ],
+ "fieldsets": [
+ {
+ "_type": "Fieldset",
+ "width": 32,
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "0",
+ "name": "RPU",
+ "description": [
+ "RPU supported.",
+ "Must only be set if RPU is supported by all masters."
+ ],
+ "values": {
+ "0b0": "Not supported",
+ "0b1": "Supported"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "3:1",
+ "name": "ENC",
+ "description": [
+ "Memory encryption support.",
+ "Must only be set to a non-zero value if supported by all Memory Controllers."
+ ],
+ "values": {
+ "0b000": "Not supported",
+ "0b001": "Global memory encryption",
+ "0b010": "Per-Realm memory encryption",
+ "0b011": "Per-page memory encryption"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "5:4",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "6",
+ "name": "INTEG",
+ "description": [
+ "Memory integrity support.",
+ "Must only be set to a non-zero value if supported by all Memory Controllers."
+ ],
+ "values": {
+ "0b0": "Not supported",
+ "0b1": "Supported"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "7",
+ "name": "ZERO",
+ "description": [
+ "Memory zeroing support.",
+ "Must only be set to a non-zero value if supported by all Memory Controllers."
+ ],
+ "values": {
+ "0b0": "Not supported",
+ "0b1": "Supported"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "8",
+ "name": "DRAM_PKG",
+ "description": "DRAM packaging.",
+ "values": {
+ "0b0": "DRAM outside package",
+ "0b1": "DRAM inside package"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "31:9",
+ "value": "RES0"
+ }
+ ]
+ }
+ ]
+}
diff --git a/json/structures/CRGTE.json b/json/structures/CRGTE.json
@@ -0,0 +1,23 @@
+{
+ "_type": "Structure",
+ "name": "CRGTE",
+ "title": "Compressed Realm Granule Table Entry (CRGTE)",
+ "fieldset": {
+ "_type": "Fieldset",
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "1:0",
+ "name": "PROPS",
+ "description": "RPG properties.",
+ "values": {
+ "0b00": "No Information (RPU needs to Read L1RGT)",
+ "0b01": "2MB Fused Default-RGTE page",
+ "0b10": "2MB Fused page which is not Default-RGTE (RPU needs to Read L1RGT)",
+ "0b11": "Reserved"
+ }
+ }
+ ],
+ "width": 2
+ }
+}
diff --git a/json/structures/L0RGTE.json b/json/structures/L0RGTE.json
@@ -0,0 +1,120 @@
+{
+ "_type": "Structure",
+ "name": "L0RGTE",
+ "title": "Level 0 Realm Granule Table Entry (L0RGTE)",
+ "fieldset": {
+ "_type": "Fieldset",
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "0",
+ "name": "VALID",
+ "description": "Indicates whether entry contents are valid.",
+ "values": {
+ "0b0": "Invalid",
+ "0b1": "Valid"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "1",
+ "name": "L1RGT_EN",
+ "description": "Level 1 RGT enable.",
+ "values": {
+ "0b0": "Disabled",
+ "0b1": "Enabled"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "2",
+ "name": "CRGT_EN",
+ "description": "Compressed RGT enable.",
+ "values": {
+ "0b0": "Disabled",
+ "0b1": "Enabled"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "7:3",
+ "name": "TYPE",
+ "description": "Entry type."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "11:8",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "51:12",
+ "name": "BADDR",
+ "description": "L1RGT base physical address, specified in 4KB granularity."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "63:52",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "77:64",
+ "name": "START",
+ "description": [
+ "L1RGT mapped region start offset, specified in 256MB granularity.",
+ "Offset is relative to the start address of the segment."
+ ]
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "79:78",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "93:80",
+ "name": "START",
+ "description": [
+ "L1RGT mapped region end offset, specified in 256MB granularity.",
+ "Offset is relative to the start address of the segment."
+ ]
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "95:94",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "96",
+ "name": "OVR_EN",
+ "description": "Default RGTE override enable.",
+ "values": {
+ "0b0": "Disabled",
+ "0b1": "Enabled"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "99:97",
+ "name": "OVR_OWNER_PERMS",
+ "description": "Default RGTE override owner access permissions.",
+ "values": { "_include": "../enums/RPG_OwnerAccessPermissions.json" }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "103:100",
+ "name": "OVR_STATE",
+ "description": "Default RGTE override state.",
+ "values": { "_include": "../enums/RPG_State.json" }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "127:104",
+ "value": "RES0"
+ }
+ ],
+ "width": 128
+ }
+}
diff --git a/json/structures/RGTE.json b/json/structures/RGTE.json
@@ -0,0 +1,134 @@
+{
+ "_type": "Structure",
+ "name": "RGTE",
+ "title": "Realm Granule Table Entry (RGTE)",
+ "fieldset": {
+ "_type": "Fieldset",
+ "values": [
+ {
+ "_type": "Fields.Field",
+ "rangeset": "3:0",
+ "name": "STATE",
+ "description": "RPG state.",
+ "values": { "_include": "../enums/RPG_State.json" }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "6:4",
+ "name": "OWNER_PERMS",
+ "description": "RPG owner access permissions.",
+ "values": { "_include": "../enums/RPG_OwnerAccessPermissions.json" }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "7",
+ "name": "VISIBILITY",
+ "description": "RPG visibility.",
+ "values": {
+ "0b0": "Owner",
+ "0b1": "Global"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "9:8",
+ "name": "GLOBAL_PERMS",
+ "description": "RPG global access permissions.",
+ "values": { "_include": "../enums/RPG_GlobalAccessPermissions.json" }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "11:10",
+ "name": "SECURE_ACCESS",
+ "description": "Reserved for TZMP."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "51:12",
+ "name": "OWNER",
+ "description": "RPG owner IRID."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "59:52",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "63:60",
+ "name": "FUSE_LEVEL",
+ "description": "RPG fuse level."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "64",
+ "name": "LOCK",
+ "description": "RPG lock.",
+ "values": {
+ "0b0": "Unlocked",
+ "0b1": "Locked"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "67:65",
+ "name": "LOCK_EXT",
+ "description": "RPG extended lock."
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "68",
+ "name": "PIN",
+ "description": "RPG pin.",
+ "values": {
+ "0b0": "Unpinned",
+ "0b1": "Pinned"
+ }
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "69",
+ "name": "INTEG",
+ "description": "RPG integrity protection.",
+ "values": {
+ "0b0": "Not integrity protected",
+ "0b1": "Integrity protected"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "70",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "72:71",
+ "name": "EXPORT_DEPTH",
+ "description": "RPG export depth.",
+ "values": {
+ "0b00": "0",
+ "0b01": "1",
+ "0b10": "Reserved",
+ "0b11": "Reserved"
+ }
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "75:73",
+ "value": "RES0"
+ },
+ {
+ "_type": "Fields.Field",
+ "rangeset": "119:76",
+ "name": "MAPPED_ADDR",
+ "description": "RPG mapped address."
+ },
+ {
+ "_type": "Fields.Reserved",
+ "rangeset": "127:120",
+ "value": "RES0"
+ }
+ ],
+ "width": 128
+ }
+}
diff --git a/json/version b/json/version
@@ -0,0 +1 @@
+15f36f5980bcccf456d4abe53efec532b2b432b9
