9os

commit 2e1e265923d926fafbc4d597196958482328a635
parent b23d88f2814f0216037df0924418c9d05bf4d378
Author: Roberto Vargas <roberto.vargas@arm.com>
Date:   Fri, 23 Nov 2018 13:45:06 +0000

[native] Fix TPIDR_R and add VBAR_R to sysreg.lst

Change-Id: I0110250c89e3809c5d604bd11e5f9db0439cd8f1

Diffstat:
M
target/native/arch.s
 | 
2
+-
M
target/native/sysreg.lst
 | 
3
++-

2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/native/arch.s b/target/native/arch.s
@@ -29,7 +29,7 @@ barrier:
 	ret
 
 bss:
-	mrs     x0,S3_6_C12_C0_6   /* TPIDR_R */
+	mrs     x0,S3_6_C13_C0_6   /* TPIDR_R */
 	ret
 
 invdcachesetway:
diff --git a/target/native/sysreg.lst b/target/native/sysreg.lst
@@ -4,7 +4,8 @@ RCR_R			S3_6_C1_C1_6
 RDSCR_R			S3_6_C6_C15_6
 SCTLR_R			S3_6_C1_C0_6
 RVBAR_EL3		S3_6_C12_C0_1
-TPIDR_R                 S3_6_C12_C0_6
+VBAR_R                  S3_6_C12_C0_6
+TPIDR_R                 S3_6_C13_C0_6
 CLIDR_EL1		S3_1_C0_C0_1
 CCSIDR_EL1		S3_1_C0_C0_0
 CSSELR_EL1		S3_2_C0_C0_0