9os

commit 24ea95212330f6eea49d2efc118c0d17000fad65
parent 80c450450a36aa3983ea8d7122e5ca91b40c6e62
Author: Roberto Vargas <roberto.vargas@arm.com>
Date:   Wed, 14 Nov 2018 11:24:02 +0000

[arch/arm64] Add system register functions

Change-Id: Id2d548b0e4817cb9e5db9f155684c9ac1c1ea7a3

Diffstat:
A
arch/arm64/arch.h
 | 
17
+++++++++++++++++
M
arch/arm64/arch.s
 | 
76
++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------
M
arch/arm64/rom-rmode.c
 | 
4
+++-
M
include/rcode.h
 | 
17
-----------------

4 files changed, 74 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/arch.h b/arch/arm64/arch.h
@@ -0,0 +1,17 @@
+enum barrier_type {
+	ISB,
+	DSB_SY,
+};
+
+enum sysreg {
+	ACTLR_R,
+	ID_AA64RMFR0_R,
+	RCR_R,
+	RDSCR_R,
+	SCTLR_R,
+	RVBAR_EL3,
+};
+
+extern void wsysreg(enum sysreg, unsigned long long v);
+extern unsigned long long rsysreg(enum sysreg);
+extern void barrier(enum barrier_type type);
diff --git a/arch/arm64/arch.s b/arch/arm64/arch.s
@@ -2,10 +2,7 @@
 
 	.text
 	.globl	panic,dohalt,enaint,dopanic
-	.globl	rd_actlr_r,wr_actlr_r
-	.globl	rd_id_aa64rmfr0_r,wr_id_aa64rmfr0_r
-	.globl	rd_rcr_r,wr_rcr_r,rd_rdscr_r,wr_rdscr_r
-	.globl	rd_sctlr_r,wr_sctlr_r,rd_rvbar_el3
+	.globl	rsysreg,wsysreg
 	.globl	barrier,vectbl,doswtch,inm8,inm16,inm32
 	.globl	outm8,outm16,outm32
 
@@ -13,50 +10,76 @@ enaint:
 	msr     daifclr,#15
 	ret
 
+/*
+ * rsysreg: write a system register
+ */
+rsysreg:
+	adr	x1, 1f
+	lsl	x0, x0, #3
+	add	x1, x1, x0
+	br	x1
+
+1:
 rd_actlr_r:
 	mrs	x0,S3_6_C1_C0_3
 	ret
 
-wr_actlr_r:
-	msr	S3_6_C1_C0_3,x0
-	ret
-
 rd_id_aa64rmfr0_r:
 	mrs	x0,S3_6_C0_C7_6
 	ret
 
-wr_id_aa64rmfr0_r:
-	msr	S3_6_C0_C7_6,x0
-	ret
-
 rd_rcr_r:
 	mrs	x0,S3_6_C1_C1_6
 	ret
 
-wr_rcr_r:
-	msr	S3_6_C1_C1_6,x0
-	ret
-
 rd_rdscr_r:
 	mrs	x0,S3_6_C6_C15_6
 	ret
 
-wr_rdscr_r:
-	msr	S3_6_C6_C15_6,x0
-	ret
-
 rd_sctlr_r:
 	mrs	x0,S3_6_C1_C0_6
 	ret
 
+rd_rvbar_el3:
+	mrs	x0,rvbar_el3
+	ret
+
+/*
+ * wsysreg: write a system register
+ */
+wsysreg:
+	adr	x1, 1f
+	lsl	x0, x0, #3
+	add	x1, x1, x0
+	br	x1
+
+1:
+wr_actlr_r:
+	msr	S3_6_C1_C0_3,x0
+	ret
+
+wr_id_aa64rmfr0_r:
+	msr	S3_6_C0_C7_6,x0
+	ret
+
+wr_rcr_r:
+	msr	S3_6_C1_C1_6,x0
+	ret
+
+wr_rdscr_r:
+	msr	S3_6_C6_C15_6,x0
+	ret
+
 wr_sctlr_r:
 	msr	S3_6_C1_C0_6,x0
 	ret
 
-rd_rvbar_el3:
-	mrs	x0,rvbar_el3
+wr_rvbar_el3:
+	b	badinst
 	ret
 
+
+
 barrier:
 	adr	x1, 1f
 	lsl	x0, x0, #3
@@ -69,6 +92,15 @@ barrier:
 	dsb	sy
 	ret
 
+badinst:
+	adr	x0,badimsg
+	b	panic
+
+	.section	.rodata
+badimsg:
+	.asciz	"invalid instruction"
+
+	.text
 inm8:
 	ldrb    w0,[x0]
 	ret
diff --git a/arch/arm64/rom-rmode.c b/arch/arm64/rom-rmode.c
@@ -3,6 +3,8 @@
 #include <rcode.h>
 #include <uart.h>
 
+#include "arch.h"
+
 void
 main(void *text, void *ram, size_t ramsiz)
 {
@@ -24,7 +26,7 @@ main(void *text, void *ram, size_t ramsiz)
 	barrier(ISB);
 
 	frame.sp = bp + ramsiz;
-	frame.elr = rd_rvbar_el3();
+	frame.elr = (void *) rsysreg(RVBAR_EL3);
 	frame.spsr = 0xf << 6 | 0xd;
 
 	dbg("romfw: text = %p, ram = %p, ramsiz = 0x%llx\n",
diff --git a/include/rcode.h b/include/rcode.h
@@ -73,11 +73,6 @@ enum ecvals {
 	NR_EC_VALS
 };
 
-enum barrier_type {
-	ISB,
-	DSB_SY,
-};
-
 #ifdef NDEBUG
 #define NR_EC_STR 0
 #else
@@ -155,18 +150,6 @@ extern _Noreturn void dohalt(void);
 extern _Noreturn void dopanic(void);
 extern _Noreturn void doswtch(struct trapframe *fp);
 extern void enaint(void);
-extern unsigned long long rd_actlr_r(void);
-extern void wr_actlr_r(unsigned long long v);
-extern unsigned long long rd_id_aa64rmfr0_r(void);
-extern void wr_id_aa64rmfr0_r(unsigned long long v);
-extern unsigned long long rd_rcr_r(void);
-extern void wr_rcr_r(unsigned long long v);
-extern unsigned long long rd_rdscr_r(void);
-extern void wr_rdscr_r(unsigned long long v);
-extern unsigned long long rd_sctlr_r(void);
-extern void wr_sctlr_r(unsigned long long v);
-extern void *rd_rvbar_el3(void);
-extern void barrier(enum barrier_type type);
 extern uint8_t inm8(void *addr);
 extern uint16_t inm16(void *addr);
 extern uint32_t inm32(void *addr);