commit 15d37b0609aad81a55e4791b03436d514d24ed07
parent 426944094b6e6acad0dd8701aa6122fb84847181
Author: Dimitris Papastamos <dimitris.papastamos@arm.com>
Date: Fri, 12 Oct 2018 16:29:21 +0100
[arm64] Rework vector table format
There was not much benefit for macros.s since we only handle sync
exceptions and each handler is only 2 instructions.
Change-Id: I75fb50748c1b7cdd73e0988bbd44dfadad217541
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Diffstat:
3 files changed, 54 insertions(+), 64 deletions(-)
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
@@ -18,7 +18,7 @@ crt-none.s: cdeps
crt-none.s: frame.inc
-ram-crt-none.o rom-crt-none.o: macros.s crt-none.s
+ram-crt-none.o rom-crt-none.o: crt-none.s
$(BINDIR)/romfw.elf: $(ROMOBJS) $(LIBDEP)
$(LD) $(RCODE_LDFLAGS) $(ROMOBJS) $(LIBS) -o $@
diff --git a/arch/arm64/crt-none.s b/arch/arm64/crt-none.s
@@ -1,4 +1,3 @@
- .include "macros.s"
.include "frame.inc"
/* TODO: extract data section address from RSCB */
@@ -43,37 +42,69 @@ _start:
ldr x0,=outsync
b panic
-outsync:
- .asciz "out of sync"
+_badtrap:
+ adr x0,unexpected
+ b panic
/* Top level arm64 Sync exception handler */
_synchdl:
- handler synchdl
+ stp x1,x0,[sp,#-16]!
+ stp x3,x2,[sp,#-16]!
+ stp x5,x4,[sp,#-16]!
+ stp x7,x6,[sp,#-16]!
+ stp x9,x8,[sp,#-16]!
+ stp x11,x10,[sp,#-16]!
+ stp x13,x12,[sp,#-16]!
+ stp x15,x14,[sp,#-16]!
+ stp x17,x16,[sp,#-16]!
+ stp x19,x18,[sp,#-16]!
+ stp x21,x20,[sp,#-16]!
+ stp x23,x22,[sp,#-16]!
+ stp x25,x24,[sp,#-16]!
+ stp x27,x26,[sp,#-16]!
+ stp x29,x28,[sp,#-16]!
+ stp xzr,x30,[sp,#-16]! /* SP = 0, only useful in panic() */
+
+ mrs x1,S3_6_C4_C0_6 /* SPSR_R */
+ mrs x0,S3_6_C4_C0_3 /* ELR_R */
+ stp x1,x0,[sp,#-16]!
+
+ mrs x1,S3_6_C6_C0_6 /* FAR_R */
+ mrs x0,S3_6_C5_C2_6 /* ESR_R */
+ stp x1,x0,[sp,#-16]!
+
+ mov x0,sp
+ bl synchdl
+ b swtch
+
+outsync:
+ .asciz "out of sync"
+
+unexpected:
+ .asciz "unexpected exception"
.align 11
vectbl:
/* Current EL with SP0 */
- vempty /* Sync */
- vempty /* IRQ/vIRQ */
- vempty /* FIQ/vFIQ */
- vempty /* SError/VSError */
+ b _badtrap; nop /* Sync */
+ b _badtrap; nop /* IRQ/vIRQ */
+ b _badtrap; nop /* FIQ/vFIQ */
+ b _badtrap; nop /* SError/VSError */
/* Current EL with SPx */
- vempty /* Sync */
- vempty /* IRQ/vIRQ */
- vempty /* FIQ/vFIQ */
- vempty /* SError/VSError */
+ b _badtrap; nop /* Sync */
+ b _badtrap; nop /* IRQ/vIRQ */
+ b _badtrap; nop /* FIQ/vFIQ */
+ b _badtrap; nop /* SError/VSError */
/* Lower EL using AArch64 */
- vector _synchdl /* Sync */
- vempty /* IRQ/vIRQ */
- vempty /* FIQ/vFIQ */
- vempty /* SError/VSError */
+ b _synchdl; nop /* Sync */
+ b _badtrap; nop /* IRQ/vIRQ */
+ b _badtrap; nop /* FIQ/vFIQ */
+ b _badtrap; nop /* SError/VSError */
/* Lower EL using AArch32 */
- vector _synchdl /* Sync */
- vempty /* IRQ/vIRQ */
- vempty /* FIQ/vFIQ */
- vempty /* SError/VSError */
-
-badtrap: .asciz "bad exception"
+ b _synchdl; nop /* Sync */
+ b _badtrap; nop /* IRQ/vIRQ */
+ b _badtrap; nop /* FIQ/vFIQ */
+ b _badtrap; nop /* SError/VSError */
diff --git a/arch/arm64/macros.s b/arch/arm64/macros.s
@@ -1,41 +0,0 @@
-.macro vempty
- .align 3
- adr x0,badtrap
- b panic
-.endm
-
-.macro vector name
- .align 3
- b \name
-.endm
-
-.macro handler target
- stp x1,x0,[sp,#-16]!
- stp x3,x2,[sp,#-16]!
- stp x5,x4,[sp,#-16]!
- stp x7,x6,[sp,#-16]!
- stp x9,x8,[sp,#-16]!
- stp x11,x10,[sp,#-16]!
- stp x13,x12,[sp,#-16]!
- stp x15,x14,[sp,#-16]!
- stp x17,x16,[sp,#-16]!
- stp x19,x18,[sp,#-16]!
- stp x21,x20,[sp,#-16]!
- stp x23,x22,[sp,#-16]!
- stp x25,x24,[sp,#-16]!
- stp x27,x26,[sp,#-16]!
- stp x29,x28,[sp,#-16]!
- stp xzr,x30,[sp,#-16]! /* SP = 0, only useful in panic() */
-
- mrs x1,S3_6_C4_C0_6 /* SPSR_R */
- mrs x0,S3_6_C4_C0_3 /* ELR_R */
- stp x1,x0,[sp,#-16]!
-
- mrs x1,S3_6_C6_C0_6 /* FAR_R */
- mrs x0,S3_6_C5_C2_6 /* ESR_R */
- stp x1,x0,[sp,#-16]!
-
- mov x0,sp
- bl \target
- b swtch
-.endm
