scc

commit f5a2ddedc976d715bd43a8667c35882c12cf3b9c
parent 386c2e594104b251c60ba48d200902628cbadc39
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Sun, 17 Dec 2017 10:10:05 +0100

[as-z80] Add SP 16 bit load instructions

These instructions allows to load a 16 bit value in SP.

Diffstat:
M
as/target/gen.awk
 | 
2
++
M
as/target/x80/ins.c
 | 
2
+-
M
as/target/x80/x80.dat
 | 
5
+++++
M
as/target/z80/proc.c
 | 
1
+

4 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/as/target/gen.awk b/as/target/gen.awk
@@ -87,6 +87,8 @@ function str2args(s, args, i, out, n)
 			out = out "AREG_A"
 		} else if (match(a, /^indir_HL/)) {
 			out = out "AINDER_HL"
+		} else if (match(a, /^regSP/)) {
+			out = out "AREG_SP"
 		} else if (match(a, /^regHL/)) {
 			out = out "AREG_HL"
 		} else if (match(a, /^regIX/)) {
diff --git a/as/target/x80/ins.c b/as/target/x80/ins.c
@@ -212,7 +212,7 @@ r16_imm16(Op *op, Node **args)
 	val = par2->sym->value;
 	buf[n-1] = val >> 8;
 	buf[n-2] = val;
-	buf[n-3] |= reg2int(par1->sym->argtype) << 3;
+	buf[n-3] |= reg2int(par1->sym->argtype) << 4;
 	emit(buf, n);
 }
 
diff --git a/as/target/x80/x80.dat b/as/target/x80/x80.dat
@@ -87,6 +87,7 @@ LD	reg_q,reg_q	2	0xfd,0x40	r8_r8	Z80,R800
 LD	indir_HL,reg_r	1	0x70	xx_r8	Z80,R800,GB80
 LD	reg_r,indir_HL	1	0x46	r8_xx	Z80,R800,GB80
 
+# 16 bit load group
 LD	reg_dd,imm16	3	0x01	r16_imm16	Z80,R800,GB80
 LD	regIX,imm16	4	0xdd,0x21	imm16	Z80,R800
 LD	regIY,imm16	4	0xfd,0x21	imm16	Z80,R800
@@ -101,6 +102,10 @@ LD	dir,reg_dd	4	0xdd,0x42	r16_dir	Z80,R800
 LD	dir,regIX	4	0xdd,0x22	dir	Z80,R800
 LD	dir,regIY	4	0xfd,0x22	dir	Z80,R800
 
+LD	regSP,regHL	1	0xf9	noargs	Z80,R800,GB80
+LD	regSP,regIX	2	0xdd,0xf9	noargs	Z80,R800
+LD	regSP,regIY	2	0xfd,0xf9	noargs	Z80,R800
+
 ADD	regA,reg_r	1	0x80	xx_r8	Z80,R800,GB80
 ADD	regA,reg_p	2	0xdd,0x80	xx_r8	Z80,R800
 ADD	regA,reg_q	2	0xfd,0x80	xx_r8	Z80,R800
diff --git a/as/target/z80/proc.c b/as/target/z80/proc.c
@@ -80,6 +80,7 @@ match(Op *op, Node **args)
 		case AREG_HL:
 		case AREG_IY:
 		case AREG_IX:
+		case AREG_SP:
 			if (np->addr != AREG || np->sym->argtype != arg)
 				return 0;
 			break;