scc

commit 971a51ce772f401beff8f4fabb224ef6a333f413
parent 83dd0b190d18e203ec666947ba8e1c1cd8ff2548
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Mon, 18 Dec 2017 14:02:38 +0000

[as-z80] Add input and output group

Diffstat:
M
as/target/gen.awk
 | 
6
++++++
M
as/target/x80/proc.h
 | 
2
++
M
as/target/x80/x80.dat
 | 
25
+++++++++++++++++--------
M
as/target/z80/proc.c
 | 
5
+++++

4 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/as/target/gen.awk b/as/target/gen.awk
@@ -105,6 +105,8 @@ function str2args(s, args, i, out, n)
 			out = out "AINDER_HL"
 		} else if (match(a, /^\(SP\)/)) {
 			out = out "AINDER_SP"
+		} else if (match(a, /^\(C\)/)) {
+			out = out "AINDER_C"
 		} else if (match(a, /^SP/)) {
 			out = out "AREG_SP"
 		} else if (match(a, /^HL/)) {
@@ -121,10 +123,14 @@ function str2args(s, args, i, out, n)
 			out = out "AREG_AF"
 		} else if (match(a, /^A/)) {
 			out = out "AREG_A"
+		} else if (match(a, /^F/)) {
+			out = out "AREG_F"
 		} else if (match(a, /^\(n\)/)) {
 			out = out "ADIRECT"
 		} else if (match(a, /^I/)) {
 			out = out "AREG_I"
+		} else if (match(a, /^0/)) {
+			out = out "AZERO"
 		} else if (match(a, /^sym/)) {
 			out = out "ASYM"
 		} else if (match(a, /^string/)) {
diff --git a/as/target/x80/proc.h b/as/target/x80/proc.h
@@ -44,8 +44,10 @@ enum args {
 	AINDER_DE,    /* (DE) */
 	AINDER_BC,    /* (BC) */
 	AINDER_SP,    /* (SP) */
+	AINDER_C,     /* (C) */
 
 	AIMM3,         /* 3 bit immediate */
+	AZERO,         /* a literal 0 */
 };
 
 extern int rclass(int reg);
diff --git a/as/target/x80/x80.dat b/as/target/x80/x80.dat
@@ -35,14 +35,6 @@
 
 RET	none	1	0xc9	noargs	Z80,R800,GB80
 
-INI 	none	2	0xed,0xa2	noargs	Z80,R800
-INIR	none	2	0xed,0xb2	noargs	Z80,R800
-IND	none	2	0xed,0xaa	noargs	Z80,R800
-INDR	none	2	0xed,0xba	noargs	Z80,R800
-OUTI	none	2	0xed,0xa3	noargs	Z80,R800
-OTIR	none	2	0xed,0xb3	noargs	Z80,R800
-OUTD	none	2	0xed,0xab	noargs	Z80,R800
-OTDR	none	2	0xed,0xbb	noargs	Z80,R800
 
 # p is any register from B, C, D, E, IXL, IXH, A
 # q is any register from B, C, D, E, IYL, IYH, A
@@ -320,3 +312,20 @@ RES	imm3,(IX+n)	4	0xdd,0xcb,0,0x86	idx_bit	Z80,R800
 RES	imm3,(IY+n)	4	0xfd,0xcb,0,0x86	idx_bit	Z80,R800
 RES	imm3,(IX+n),r	4	0xdd,0xcb,0,0x80	r_idx_bit	Z80,R800
 RES	imm3,(IY+n),r	4	0xfd,0xcb,0,0x80	r_idx_bit	Z80,R800
+
+# Input and output group
+IN	A,(n)	2	0xdb	imm8	Z80,R800
+IN	r,(C)	2	0xed,0x40	r8_xx	Z80,R800
+IN	F,(C)	2	0xed,0x70	noargs	Z80,R800
+INI 	none	2	0xed,0xa2	noargs	Z80,R800
+INIR	none	2	0xed,0xb2	noargs	Z80,R800
+IND	none	2	0xed,0xaa	noargs	Z80,R800
+INDR	none	2	0xed,0xba	noargs	Z80,R800
+
+OUT	(n),A	2	0xd3	imm8	Z80,R800
+OUT	(C),r	2	0xed,0x41	r8_xx	Z80,R800
+OUT	(C),0	2	0xed,0x71	noargs	Z80,R800
+OUTI	none	2	0xed,0xa3	noargs	Z80,R800
+OTIR	none	2	0xed,0xb3	noargs	Z80,R800
+OUTD	none	2	0xed,0xab	noargs	Z80,R800
+OTDR	none	2	0xed,0xbb	noargs	Z80,R800
diff --git a/as/target/z80/proc.c b/as/target/z80/proc.c
@@ -70,6 +70,9 @@ match(Op *op, Node **args)
 
 		arg &= ~(AREP|AOPT);
 		switch (arg) {
+		case AINDER_C:
+			arg = AREG_C;
+			goto indirect;
 		case AINDER_HL:
 			arg = AREG_HL;
 			goto indirect;
@@ -86,6 +89,7 @@ match(Op *op, Node **args)
 				return 0;
 			np = np->left;
 		case AREG_A:
+		case AREG_F:
 		case AREG_HL:
 		case AREG_DE:
 		case AREG_IY:
@@ -133,6 +137,7 @@ match(Op *op, Node **args)
 			if (np->left->left->sym->argtype != arg)
 				return 0;
 			break;
+		case AZERO:
 		case AIMM3:
 		case AIMM8:
 		case AIMM16: