scc

commit 6dfb4783f04f04a17c849cfa3df9dbc221681e78
parent 30471dba4dfb45f4f8fe02f6fab4608502abb5c1
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Sun, 17 Dec 2017 22:45:55 +0100

[as-z80] Add 16 bit ALU group

Diffstat:
M
as/target/gen.awk
 | 
4
++++
M
as/target/x80/ins.c
 | 
28
++++++++++++++++++++++++++++
M
as/target/x80/proc.h
 | 
4
++++
M
as/target/x80/x80.dat
 | 
17
+++++++++++++++++
M
as/target/z80/proc.c
 | 
6
++++++

5 files changed, 59 insertions(+), 0 deletions(-)
diff --git a/as/target/gen.awk b/as/target/gen.awk
@@ -83,6 +83,10 @@ function str2args(s, args, i, out, n)
 			out = out "AREG_DDCLASS"
 		} else if (match(a, /^qq/)) {
 			out = out "AREG_QQCLASS"
+		} else if (match(a, /^rr/)) {
+			out = out "AREG_RRCLASS"
+		} else if (match(a, /^pp/)) {
+			out = out "AREG_PPCLASS"
 		} else if (match(a, /^p/)) {
 			out = out "AREG_PCLASS"
 		} else if (match(a, /^q/)) {
diff --git a/as/target/x80/ins.c b/as/target/x80/ins.c
@@ -86,6 +86,34 @@ qqclass(int reg)
 	}
 }
 
+int
+ppclass(int reg)
+{
+	switch (reg) {
+	case AREG_BC:
+	case AREG_DE:
+	case AREG_IX:
+	case AREG_SP:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+int
+rrclass(int reg)
+{
+	switch (reg) {
+	case AREG_BC:
+	case AREG_DE:
+	case AREG_IY:
+	case AREG_SP:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
 static int
 reg2int(int reg)
 {
diff --git a/as/target/x80/proc.h b/as/target/x80/proc.h
@@ -34,6 +34,8 @@ enum args {
 	AREG_QCLASS,  /* register class for B, C, D, E, IYH, IYL and A */
 	AREG_DDCLASS, /* register class for BC, DE, HL and SP */
 	AREG_QQCLASS, /* register class for BC, DE, HL and AF */
+	AREG_PPCLASS, /* register class for BC, DE, IX and SP */
+	AREG_RRCLASS, /* register class for BC, DE, IY and SP */
 
 	AINDEX_IX,    /* (IX+d) */
 	AINDEX_IY,    /* (IX+d) */
@@ -48,3 +50,5 @@ extern int pclass(int reg);
 extern int qclass(int reg);
 extern int ddclass(int reg);
 extern int qqclass(int reg);
+extern int ppclass(int reg);
+extern int rrclass(int reg);
diff --git a/as/target/x80/x80.dat b/as/target/x80/x80.dat
@@ -76,6 +76,8 @@ OTDR	none	2	0xed,0xbb	noargs	Z80,R800
 # r is any register from B, C, D, E, L, H, A
 # dd is any register from BC, DE, HL, SP
 # qq is any register from BC, DE, HL, AF
+# pp is any register from BC, DE, IX, SP
+# rr is any register from BC, DE, IY, SP
 
 # 8 bit load group
 LD	r,imm8	2	0x06	r8_imm8	Z80,R800,GB80
@@ -215,3 +217,18 @@ DEC	q	2	0xfd,0x05	r8	Z80,R800
 DEC	(HL)	1	0x35	noargs	Z80,R800,GB80
 DEC	(IX+n)	3	0xdd,0x35	idx	Z80,R800
 DEC	(IY+n)	3	0xfd,0x35	idx	Z80,R800
+
+# 16 bit ALU group
+ADD	HL,dd	1	0x09	r16	Z80,R800,GB80
+ADC	HL,dd	2	0xed,0x4a	r16	Z80,R800
+SBC	HL,dd	2	0xed,0x42	r16	Z80,R800
+ADD	IX,pp	2	0xdd,0x09	r16	Z80,R800
+ADD	IY,rr	2	0xfd,0x09	r16	Z80,R800
+
+INC	dd	1	0x03	r16	Z80,R800,GB80
+INC	IX	2	0xdd,0x23	noargs	Z80,R800
+INC	IY	2	0xfd,0x23	noargs	Z80,R800
+
+DEC	dd	1	0x0b	r16	Z80,R800,GB80
+DEC	IX	2	0xdd,0x2b	noargs	Z80,R800
+DEC	IY	2	0xfd,0x2b	noargs	Z80,R800
diff --git a/as/target/z80/proc.c b/as/target/z80/proc.c
@@ -96,6 +96,12 @@ match(Op *op, Node **args)
 		case AREG_QQCLASS:
 			class = qqclass;
 			goto register_class;
+		case AREG_PPCLASS:
+			class = ppclass;
+			goto register_class;
+		case AREG_RRCLASS:
+			class = rrclass;
+			goto register_class;
 		case AREG_DDCLASS:
 			class = ddclass;
 		register_class: