commit d53d0f8403906e49d3a8883f77fb9445bb0128b4
parent 13e5e0ad5a64cc0d35e641044949679f6b5c6c20
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date: Fri, 18 Sep 2020 17:28:29 +0200
aarch64: Use upper case for asm
This is traditional asm style.
Change-Id: I3209e9d768d00ba33b3db67c955f54c0f860ed9b
Diffstat:
4 files changed, 245 insertions(+), 245 deletions(-)
diff --git a/src/os9/arch/arm64/arch.s b/src/os9/arch/arm64/arch.s
@@ -1,217 +1,217 @@
- .file "arch.s"
+ .FILE "arch.s"
- .text
- .globl panic,halt,intr,swtch,getcontext
- .globl barrier,vectbl,doswtch,inm8,inm16,inm32
- .globl outm8,outm16,outm32
- .globl invdcachesetway,invicache,vectbl
- .globl inm8,inm16,inm32,outm8,outm16,outm32
+ .TEXT
+ .GLOBL panic,halt,intr,swtch,getcontext
+ .GLOBL barrier,vectbl,doswtch,inm8,inm16,inm32
+ .GLOBL outm8,outm16,outm32
+ .GLOBL invdcachesetway,invicache,vectbl
+ .GLOBL inm8,inm16,inm32,outm8,outm16,outm32
intr:
- cmp x0,#0
- b.ne 1f
- msr daifset,#15
- ret
+ CMP X0,#0
+ B.NE 1f
+ MSR DAIFSET,#15
+ RET
1:
- msr daifclr,#15
- ret
+ MSR DAIFCLR,#15
+ RET
barrier:
- adr x1,1f
- lsl x0,x0,#3
- add x1,x1,x0
- br x1
+ ADR X1,1f
+ LSL X0,X0,#3
+ ADD X1,X1,X0
+ BR X1
1:
- isb
- ret
- dsb sy
- ret
+ ISb
+ RET
+ DSB SY
+ RET
invdcachesetway:
- dc isw,x0
- ret
+ DC ISW,X0
+ RET
invicache:
- ic iallu
- ret
+ IC IALLU
+ RET
badinst:
- adr x0,badimsg
- b panic
+ ADR X0,badimsg
+ B panic
- .section .rodata
+ .SECTION .rodata
badimsg:
- .asciz "invalid instruction"
+ .ASCIZ "invalid instruction"
- .text
+ .TEXT
inm8:
- ldrb w0,[x0]
- ret
+ LDRB W0,[X0]
+ RET
inm16:
- ldrh w0,[x0]
- ret
+ LDRH W0,[X0]
+ RET
inm32:
- ldr w0,[x0]
- ret
+ LDR W0,[X0]
+ RET
outm8:
- strb w0,[x1]
- ret
+ STRB W0,[X1]
+ RET
outm16:
- strh w0,[x1]
- ret
+ STRH W0,[X1]
+ RET
outm32:
- str w0,[x1]
- ret
+ STR W0,[X1]
+ RET
halt:
- msr daifset,#15
- wfe
- b halt
+ MSR DAIFSET,#15
+ WFE
+ B halt
getcontext:
- stp x0,x1,[x0,#16*0]
- stp x2,x3,[x0,#16*1]
- stp x4,x5,[x0,#16*2]
- stp x6,x7,[x0,#16*3]
- stp x8,x9,[x0,#16*4]
- stp x10,x11,[x0,#16*5]
- stp x12,x13,[x0,#16*6]
- stp x14,x15,[x0,#16*7]
- stp x16,x17,[x0,#16*8]
- stp x18,x19,[x0,#16*9]
- stp x20,x21,[x0,#16*10]
- stp x22,x23,[x0,#16*11]
- stp x24,x25,[x0,#16*12]
- stp x26,x27,[x0,#16*13]
- stp x28,x29,[x0,#16*14]
-
- mrs x9,ELR_EL1
- stp x9,x30,[x0,#16*15]
-
- mrs x9,SPSR_EL1
- mrs x10,ESR_EL1
- stp x9,x10,[x0,#16*16]
-
- mov x9,sp
- mrs x10,FAR_EL1
- stp x9,x10,[x0,#16*17]
-
- ret
+ STP X0,X1,[X0,#16*0]
+ STP X2,X3,[X0,#16*1]
+ STP X4,X5,[X0,#16*2]
+ STP X6,X7,[X0,#16*3]
+ STP X8,X9,[X0,#16*4]
+ STP X10,X11,[X0,#16*5]
+ STP X12,X13,[X0,#16*6]
+ STP X14,X15,[X0,#16*7]
+ STP X16,X17,[X0,#16*8]
+ STP X18,X19,[X0,#16*9]
+ STP X20,X21,[X0,#16*10]
+ STP X22,X23,[X0,#16*11]
+ STP X24,X25,[X0,#16*12]
+ STP X26,X27,[X0,#16*13]
+ STP X28,X29,[X0,#16*14]
+
+ MRS X9,ELR_EL1
+ STP X9,X30,[X0,#16*15]
+
+ MRS X9,SPSR_EL1
+ MRS X10,ESR_EL1
+ STP X9,X10,[X0,#16*16]
+
+ MOV X9,SP
+ MRS X10,FAR_EL1
+ STP X9,X10,[X0,#16*17]
+
+ RET
exception:
- msr spsel,#1
- stp x0,x1,[sp,#-16*(17-0)]
- stp x2,x3,[sp,#-16*(17-1)]
- stp x4,x5,[sp,#-16*(17-2)]
- stp x6,x7,[sp,#-16*(17-3)]
- stp x8,x9,[sp,#-16*(17-4)]
- stp x10,x11,[sp,#-16*(17-5)]
- stp x12,x13,[sp,#-16*(17-6)]
- stp x14,x15,[sp,#-16*(17-7)]
- stp x16,x17,[sp,#-16*(17-8)]
- stp x18,x19,[sp,#-16*(17-9)]
- stp x20,x21,[sp,#-16*(17-10)]
- stp x22,x23,[sp,#-16*(17-11)]
- stp x24,x25,[sp,#-16*(17-12)]
- stp x26,x27,[sp,#-16*(17-13)]
- stp x28,x29,[sp,#-16*(17-14)]
-
- mrs x9,ELR_EL1
- stp x9,x30,[sp,#-16*(17-15)]
-
- mrs x9,SPSR_EL1
- mrs x10,ESR_EL1
- stp x9,x10,[sp,#-16*(17-16)]
-
- mov x9,sp
- mrs x10,FAR_EL1
- stp x9,x10,[sp,#-16*(17-17)]
-
- sub sp,sp,#16*17
- mov x0,sp
- mov x29,#0
- bl trap
- adr x0,outsync
- b panic
-
- .section .rodata
+ MSR SPSEL,#1
+ STP X0,X1,[SP,#-16*(17-0)]
+ STP X2,X3,[SP,#-16*(17-1)]
+ STP X4,X5,[SP,#-16*(17-2)]
+ STP X6,X7,[SP,#-16*(17-3)]
+ STP X8,X9,[SP,#-16*(17-4)]
+ STP X10,X11,[SP,#-16*(17-5)]
+ STP X12,X13,[SP,#-16*(17-6)]
+ STP X14,X15,[SP,#-16*(17-7)]
+ STP X16,X17,[SP,#-16*(17-8)]
+ STP X18,X19,[SP,#-16*(17-9)]
+ STP X20,X21,[SP,#-16*(17-10)]
+ STP X22,X23,[SP,#-16*(17-11)]
+ STP X24,X25,[SP,#-16*(17-12)]
+ STP X26,X27,[SP,#-16*(17-13)]
+ STP X28,X29,[SP,#-16*(17-14)]
+
+ MRS X9,ELR_EL1
+ STP X9,X30,[SP,#-16*(17-15)]
+
+ MRS X9,SPSR_EL1
+ MRS X10,ESR_EL1
+ STP X9,X10,[SP,#-16*(17-16)]
+
+ MOV X9,SP
+ MRS X10,FAR_EL1
+ STP X9,X10,[SP,#-16*(17-17)]
+
+ SUB SP,SP,#16*17
+ MOV X0,SP
+ MOV X29,#0
+ BL trap
+ ADR X0,outsync
+ B panic
+
+ .DATA
outsync:
- .asciz "out of sync"
+ .ASCIZ "out of sync"
- .text
+ .TEXT
swtch:
- ldp x9,x10,[x0,#16*17]
- msr FAR_EL1,x10
- mov sp,x9
-
- ldp x9,x10,[x0,#16*16]
- msr ESR_EL1,x10
- msr SPSR_EL1,x9
-
- ldp x9,x30,[x0,#16*15]
- msr ELR_EL1,x9
-
- ldp x28,x29,[x0,#16*14]
- ldp x26,x27,[x0,#16*13]
- ldp x24,x25,[x0,#16*12]
- ldp x22,x23,[x0,#16*11]
- ldp x20,x21,[x0,#16*10]
- ldp x18,x19,[x0,#16*9]
- ldp x16,x17,[x0,#16*8]
- ldp x14,x15,[x0,#16*7]
- ldp x12,x13,[x0,#16*6]
- ldp x10,x11,[x0,#16*5]
- ldp x8,x9,[x0,#16*4]
- ldp x6,x7,[x0,#16*3]
- ldp x4,x5,[x0,#16*2]
- ldp x2,x3,[x0,#16*1]
- ldp x0,x1,[x0,#16*0]
-
- eret
-
- .align 11
+ LDP X9,X10,[X0,#16*17]
+ MSR FAR_EL1,X10
+ MOV SP,X9
+
+ LDP X9,X10,[X0,#16*16]
+ MSR ESR_EL1,X10
+ MSR SPSR_EL1,X9
+
+ LDP X9,X30,[X0,#16*15]
+ MSR ELR_EL1,X9
+
+ LDP X28,X29,[X0,#16*14]
+ LDP X26,X27,[X0,#16*13]
+ LDP X24,X25,[X0,#16*12]
+ LDP X22,X23,[X0,#16*11]
+ LDP X20,X21,[X0,#16*10]
+ LDP X18,X19,[X0,#16*9]
+ LDP X16,X17,[X0,#16*8]
+ LDP X14,X15,[X0,#16*7]
+ LDP X12,X13,[X0,#16*6]
+ LDP X10,X11,[X0,#16*5]
+ LDP X8,X9,[X0,#16*4]
+ LDP X6,X7,[X0,#16*3]
+ LDP X4,X5,[X0,#16*2]
+ LDP X2,X3,[X0,#16*1]
+ LDP X0,X1,[X0,#16*0]
+
+ ERET
+
+ .ALIGN 11
vectbl:
/* Current EL with SP0 */
- b exception /* Sync */
- .align 7
- b exception /* IRQ/vIRQ */
- .align 7
- b exception /* FIQ/vFIQ */
- .align 7
- b exception /* SError/VSError */
+ B exception /* Sync */
+ .ALIGN 7
+ B exception /* IRQ/vIRQ */
+ .ALIGN 7
+ B exception /* FIQ/vFIQ */
+ .ALIGN 7
+ B exception /* SError/VSError */
/* Current EL with SPx */
- .align 7
- b exception /* Sync */
- .align 7
- b exception /* IRQ/vIRQ */
- .align 7
- b exception /* FIQ/vFIQ */
- .align 7
- b exception /* SError/VSError */
+ .ALIGN 7
+ B exception /* Sync */
+ .ALIGN 7
+ B exception /* IRQ/vIRQ */
+ .ALIGN 7
+ B exception /* FIQ/vFIQ */
+ .ALIGN 7
+ B exception /* SError/VSError */
/* Lower EL using AArch64 */
- .align 7
- b exception /* Sync */
- .align 7
- b exception /* IRQ/vIRQ */
- .align 7
- b exception /* FIQ/vFIQ */
- .align 7
- b exception /* SError/VSError */
+ .ALIGN 7
+ B exception /* Sync */
+ .ALIGN 7
+ B exception /* IRQ/vIRQ */
+ .ALIGN 7
+ B exception /* FIQ/vFIQ */
+ .ALIGN 7
+ B exception /* SError/VSError */
/* Lower EL using AArch32 */
- .align 7
- b exception /* Sync */
- .align 7
- b exception /* IRQ/vIRQ */
- .align 7
- b exception /* FIQ/vFIQ */
- .align 7
- b exception /* SError/VSError */
+ .ALIGN 7
+ B exception /* Sync */
+ .ALIGN 7
+ B exception /* IRQ/vIRQ */
+ .ALIGN 7
+ B exception /* FIQ/vFIQ */
+ .ALIGN 7
+ B exception /* SError/VSError */
diff --git a/src/os9/arch/arm64/crt.s b/src/os9/arch/arm64/crt.s
@@ -1,62 +1,62 @@
- .file "crt.s"
- .text
- .globl _start
+ .FILE "crt.s"
+ .TEXT
+ .GLOBL _start
_start:
- mrs x0,CurrentEL
- ubfx x0,x0,#2,#2
- cmp x0,1
- beq el1
+ MRS X0,CURRENTEL
+ UBFX X0,X0,#2,#2
+ CMP X0,1
+ BEQ el1
/* small bootloader for fvp */
- ldr w0,=0x3c5
- msr SPSR_EL2,x0
+ LDR W0,=0x3C5
+ MSR SPSR_EL2,X0
- ldr w0,=0x30D00830
- msr SCTLR_EL1,x0
+ LDR W0,=0x30D00830
+ MSR SCTLR_EL1,X0
- ldr w0,=0x80000000
- msr HCR_EL2,x0
+ LDR W0,=0x80000000
+ MSR HCR_EL2,X0
- ldr x0,=_start
- msr ELR_EL2,x0
- eret
+ LDR X0,=_start
+ MSR ELR_EL2,X0
+ ERET
el1:
- adr x0,vectbl
- msr VBAR_EL1,x0
- isb
+ ADR X0,vectbl
+ MSR VBAR_EL1,X0
+ ISB
/* Differentiate between cold and warm boot (FVP only) */
- mrs x2,mpidr_el1
- ldr x1,=0x1c100000
- str w2,[x1,0x10]
- ldr w2,[x1,0x10]
- ubfx w2,w2,24,2
- cmp w2,2
- beq warm
- cmp w2,3
- beq warm
-
- ldr x0,=0x880080000 /* Set initial stack */
- mov sp,x0
-
- ldr x0,=edata /* BSS clean */
- mov x1,#0
- ldr x2,=end
- sub x2,x2,x0
- bl memset
-
- sub x29,x29,x29
- bl main
- adr x0,outsync
- b panic
+ MRS X2,MPIDR_EL1
+ LDR X1,=0x1C100000
+ STR W2,[X1,0x10]
+ LDR W2,[X1,0x10]
+ UBFX W2,W2,24,2
+ CMP W2,2
+ BEQ warm
+ CMP W2,3
+ BEQ warm
+
+ LDR X0,=0x880080000 /* Set initial stack */
+ MOV SP,X0
+
+ LDR X0,=edata /* BSS clean */
+ MOV X1,#0
+ LDR X2,=end
+ SUB X2,X2,X0
+ BL memset
+
+ SUB X29,X29,X29
+ BL main
+ ADR X0,outsync
+ B panic
warm:
/* Hardcoded address of BL2 at EL3 */
- ldr x0,=0x4022000
- br x0
+ LDR X0,=0x4022000
+ BR X0
- .section .rodata
+ .SECTION .rodata
outsync:
- .asciz "out of sync"
+ .ASCIZ "out of sync"
diff --git a/src/os9/arch/arm64/lock.s b/src/os9/arch/arm64/lock.s
@@ -1,4 +1,4 @@
-.globl lock,unlock,trylock
+ .GLOBL lock,unlock,trylock
/*
* Those functions are currently not used for two reasons:
@@ -6,21 +6,21 @@
* 2- We are executing only one execution thread.
*/
-lock:
- mov w2,#1
- sevl
+LOCK:
+ MOV W2,#1
+ SEVL
1:
- wfe
- mov w1,wzr
- casa w1,w2,[x0]
- cbnz w1,1b
- ret
+ WFE
+ MOV W1,WZR
+ CASA W1,W2,[x0]
+ CBNZ W1,1B
+ RET
unlock:
- stlr wzr,[x0]
- sev
- ret
+ STLR WZR,[X0]
+ SEV
+ RET
trylock: // TODO: implement trylock
- mov w0,#1
- ret
+ MOV W0,#1
+ RET
diff --git a/src/os9/arch/arm64/mksysreg b/src/os9/arch/arm64/mksysreg
@@ -16,26 +16,26 @@ do
-s)
shift
cat <<EOF > $$.tmp && mv $$.tmp sysreg.s
- .file "sysreg.s"
+ .FILE "sysreg.s"
- .text
- .globl rsysreg,wsysreg
+ .TEXT
+ .GLOBL rsysreg,wsysreg
rsysreg:
- adr x1,1f
- lsl x0,x0,#3
- add x1,x1,x0
- br x1
+ ADR X1,1f
+ LSL X0,X0,#3
+ ADD X1,X1,X0
+ BR X1
1:
-$(awk 'NF == 2 {printf "\tmrs\tx0,%s\n\tret\n\n", $2}' $@)
+$(awk 'NF == 2 {printf "\tMRS\tX0,%s\n\tret\n\n", $2}' $@)
wsysreg:
- adr x2,1f
- lsl x0,x0,#3
- add x2,x2,x0
- br x2
+ ADR X2,1f
+ LSL X0,X0,#3
+ ADD X2,X2,X0
+ BR X2
1:
-$(awk 'NF == 2 {printf "\tmsr\t%s,x1\n\tret\n\n", $2}' $@)
+$(awk 'NF == 2 {printf "\tMSR\t%s,X1\n\tRET\n\n", $2}' $@)
EOF
;;
esac
