9os

commit aff04880be7d7c5e6ee9efcfec213d12148c99bd
parent 1c78e134cdce606a2d56b0a925b0ac3ce387213b
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Sat, 24 Oct 2020 08:39:51 +0200

os9/arm64: Temporary solution for tlb invalidation

There is a problem with the function invtlb() because it generates
an exception when it uses a DC CVAU instruction. There is some kind
of problem with the coherence because the model does not see the
last write done in the page table just before the clean instruction
(observed using FVP).

Change-Id: I4db16ec18406388cb870c96a4599a6e15f069963

Diffstat:
M
src/os9/arch/arm64/arch.s
 | 
2
+-
M
src/os9/arch/arm64/mmu.c
 | 
5
++++-
M
src/os9/arch/arm64/trap.c
 | 
2
+-

3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/os9/arch/arm64/arch.s b/src/os9/arch/arm64/arch.s
@@ -39,7 +39,7 @@ invtlb:
 	LSR	X9,X0,#12
 	DSB	ISHST
 	TLBI	VAE1,X9
-	DC	CVAU,X0
+//	DC	CVAU,X0	// FIXME: line commented because it generates an exception
 	DSB	ISH
 	RET
 
diff --git a/src/os9/arch/arm64/mmu.c b/src/os9/arch/arm64/mmu.c
@@ -162,7 +162,7 @@ walker(uintptr_t va)
 		bp = (pte_t *) MASK(e);
 	}
 
-	dbg("va = %llx, level=%d, n=%d\n", va, 3, TINDEX(3, va));
+	dbg("va = %llx, level=%d, bp=%p, n=%d, e=%llx\n", va, 3, &bp[TINDEX(3, va)], TINDEX(3, va), bp[TINDEX(3, va)]);
 	return &bp[TINDEX(3, va)];
 }
 
@@ -198,6 +198,9 @@ vmap(phyaddr_t pa, uintptr_t va, int perm)
 	barrier(DATA);
 
 	*p = MASK(pa) | attr;
+	barrier(DATA);
+	barrier(CODE);
+
 	invtlb(va);
 	unlock(&m);
 
diff --git a/src/os9/arch/arm64/trap.c b/src/os9/arch/arm64/trap.c
@@ -21,7 +21,7 @@ trap(Context *ctx)
 
 	ec = (ctx->r[ESR] >> 26) & 0x3f;
 
-	if (ec != SVC) {
+	if (ec != SVC || inlowmem) {
 		msg = (ec < NR_EC_VALS) ? ecstr[ec] : "unknown reason";
 		if (inlowmem)
 			msg -= mach.kzero;