9os

commit 53ac88c0ea18708197a378ce6f94bd2e95347f33
parent 847cb68354e765133693f43d75f5a24cfbda338c
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Fri, 18 Sep 2020 15:16:32 +0200

aarch64: Fix getcontext() and exception()

After changing the number of registers saved because
SCR_EL3 does not have an equivalent in EL1, the asm
code written to save and restore the context could
not work anymore as the offsets are different.

Change-Id: Icc395058b7d0cb219e447dbea912d36bdc9bddea

Diffstat:
M
src/os9/arch/arm64/arch.s
 | 
74
+++++++++++++++++++++++++++++++++++++-------------------------------------

1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/src/os9/arch/arm64/arch.s b/src/os9/arch/arm64/arch.s
@@ -75,65 +75,65 @@ halt:
 	b	halt
 
 getcontext:
-	stp	x0,x1,[x0,#-16*(19-0)]
-	stp	x2,x3,[x0,#-16*(19-1)]
-	stp	x4,x5,[x0,#-16*(19-2)]
-	stp	x6,x7,[x0,#-16*(19-3)]
-	stp	x8,x9,[x0,#-16*(19-4)]
-	stp	x10,x11,[x0,#-16*(19-5)]
-	stp	x12,x13,[x0,#-16*(19-6)]
-	stp	x14,x15,[x0,#-16*(19-7)]
-	stp	x16,x17,[x0,#-16*(19-8)]
-	stp	x18,x19,[x0,#-16*(19-9)]
-	stp	x20,x21,[x0,#-16*(19-10)]
-	stp	x22,x23,[x0,#-16*(19-11)]
-	stp	x24,x25,[x0,#-16*(19-12)]
-	stp	x26,x27,[x0,#-16*(19-13)]
-	stp	x28,x29,[x0,#-16*(19-14)]
+	stp	x0,x1,[x0,#16*0]
+	stp	x2,x3,[x0,#16*1]
+	stp	x4,x5,[x0,#16*2]
+	stp	x6,x7,[x0,#16*3]
+	stp	x8,x9,[x0,#16*4]
+	stp	x10,x11,[x0,#16*5]
+	stp	x12,x13,[x0,#16*6]
+	stp	x14,x15,[x0,#16*7]
+	stp	x16,x17,[x0,#16*8]
+	stp	x18,x19,[x0,#16*9]
+	stp	x20,x21,[x0,#16*10]
+	stp	x22,x23,[x0,#16*11]
+	stp	x24,x25,[x0,#16*12]
+	stp	x26,x27,[x0,#16*13]
+	stp	x28,x29,[x0,#16*14]
 
 	mrs	x9,ELR_EL1
-	stp	x9,x30,[x0,#-16*(19-15)]
+	stp	x9,x30,[x0,#16*15]
 
 	mrs	x9,SPSR_EL1
 	mrs	x10,ESR_EL1
-	stp	x9,x10,[x0,#-16*(19-16)]
+	stp	x9,x10,[x0,#16*16]
 
 	mov	x9,sp
 	mrs	x10,FAR_EL1
-	stp	x9,x10,[x0,#-16*(19-17)]
+	stp	x9,x10,[x0,#16*17]
 
 	ret
 
 exception:
 	msr	spsel,#1
-	stp	x0,x1,[sp,#-16*(19-0)]
-	stp	x2,x3,[sp,#-16*(19-1)]
-	stp	x4,x5,[sp,#-16*(19-2)]
-	stp	x6,x7,[sp,#-16*(19-3)]
-	stp	x8,x9,[sp,#-16*(19-4)]
-	stp	x10,x11,[sp,#-16*(19-5)]
-	stp	x12,x13,[sp,#-16*(19-6)]
-	stp	x14,x15,[sp,#-16*(19-7)]
-	stp	x16,x17,[sp,#-16*(19-8)]
-	stp	x18,x19,[sp,#-16*(19-9)]
-	stp	x20,x21,[sp,#-16*(19-10)]
-	stp	x22,x23,[sp,#-16*(19-11)]
-	stp	x24,x25,[sp,#-16*(19-12)]
-	stp	x26,x27,[sp,#-16*(19-13)]
-	stp	x28,x29,[sp,#-16*(19-14)]
+	stp	x0,x1,[sp,#-16*(17-0)]
+	stp	x2,x3,[sp,#-16*(17-1)]
+	stp	x4,x5,[sp,#-16*(17-2)]
+	stp	x6,x7,[sp,#-16*(17-3)]
+	stp	x8,x9,[sp,#-16*(17-4)]
+	stp	x10,x11,[sp,#-16*(17-5)]
+	stp	x12,x13,[sp,#-16*(17-6)]
+	stp	x14,x15,[sp,#-16*(17-7)]
+	stp	x16,x17,[sp,#-16*(17-8)]
+	stp	x18,x19,[sp,#-16*(17-9)]
+	stp	x20,x21,[sp,#-16*(17-10)]
+	stp	x22,x23,[sp,#-16*(17-11)]
+	stp	x24,x25,[sp,#-16*(17-12)]
+	stp	x26,x27,[sp,#-16*(17-13)]
+	stp	x28,x29,[sp,#-16*(17-14)]
 
 	mrs	x9,ELR_EL1
-	stp	x9,x30,[sp,#-16*(19-15)]
+	stp	x9,x30,[sp,#-16*(17-15)]
 
 	mrs	x9,SPSR_EL1
 	mrs	x10,ESR_EL1
-	stp	x9,x10,[sp,#-16*(19-16)]
+	stp	x9,x10,[sp,#-16*(17-16)]
 
 	mov	x9,sp
 	mrs	x10,FAR_EL1
-	stp	x9,x10,[sp,#-16*(19-17)]
+	stp	x9,x10,[sp,#-16*(17-17)]
 
-	sub	sp,sp,#16*19
+	sub	sp,sp,#16*17
 	mov	x0,sp
 	mov	x29,#0
 	bl	trap