commit 4f99279eefda528df0ecafdd206d51e0f4478f5b
parent 05136086b8ab20eea80da672565a335c31a250fc
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date: Sun, 27 Sep 2020 11:06:23 +0200
os9/arm64: Improve architecture functions
Change-Id: Id7f2997168c70d4eac0485093d54a3f818b75c3d
Diffstat:
5 files changed, 61 insertions(+), 40 deletions(-)
diff --git a/include/os9/os9.h b/include/os9/os9.h
@@ -20,8 +20,8 @@
#define LINELEN 80
#define PAGESIZE 4096
-#define IENABLE 1
-#define IDISABLE 0
+#define ENABLE 1
+#define DISABLE 0
typedef struct context Context;
typedef struct proc Proc;
@@ -166,7 +166,7 @@ extern void dumpregs(Context *ctx, int fd);
/* architectural functions */
extern Context *getcontext(Context *ctx);
extern void *alloc(size_t size);
-extern void intr(int mode);
+extern void interrupt(int);
extern uint8_t inm8(void *addr);
extern uint16_t inm16(void *addr);
extern uint32_t inm32(void *addr);
@@ -185,7 +185,6 @@ extern Task *gettask(Proc *, int);
extern void sched(void);
/* globals */
-extern unsigned in_debug;
extern jmp_buf dbgrecover;
extern const char *const regnames[];
diff --git a/src/os9/arch/arm64/arch.h b/src/os9/arch/arm64/arch.h
@@ -89,8 +89,8 @@ struct mach {
};
extern void main(Mach *);
-extern void syswr(enum sysreg, unsigned long long);
-extern unsigned long long sysrd(enum sysreg);
+extern void syswr(int, unsigned long long);
+extern unsigned long long sysrd(int);
extern void barrier(int);
extern void invdcachesetway(void *);
extern void invdcache(void);
diff --git a/src/os9/arch/arm64/arch.s b/src/os9/arch/arm64/arch.s
@@ -1,13 +1,8 @@
.FILE "arch.s"
- .GLOBL panic,halt,intr,swtch,getcontext
- .GLOBL barrier,vectbl,doswtch,inm8,inm16,inm32
- .GLOBL outm8,outm16,outm32
- .GLOBL invdcachesetway,invicache,vectbl,invtlb
- .GLOBL inm8,inm16,inm32,outm8,outm16,outm32
-
.TEXT
-intr:
+ .GLOBL interrupt
+interrupt:
CBNZ X0,1f
MSR DAIFSET,#15
RET
@@ -15,6 +10,8 @@ intr:
MSR DAIFCLR,#15
RET
+ .TEXT
+ .GLOBL barrier
barrier:
ADR X1,1f
LSL X0,X0,#3
@@ -28,48 +25,70 @@ barrier:
DSB SY
RET
+ .TEXT
+ .GLOBL invtlb
invtlb:
TLBI VMALLE1IS
RET
+ .TEXT
+ .GLOBL invdcachesetway
invdcachesetway:
DC ISW,X0
RET
+ .TEXT
+ .GLOBL invicache
invicache:
IC IALLU
RET
+ .TEXT
+ .GLOBL inm8
inm8:
LDRB W0,[X0]
RET
+ .TEXT
+ .GLOBL inm16
inm16:
LDRH W0,[X0]
RET
+ .TEXT
+ .GLOBL inm32
inm32:
LDR W0,[X0]
RET
+ .TEXT
+ .GLOBL outm8
outm8:
STRB W0,[X1]
RET
+ .TEXT
+ .GLOBL outm16
outm16:
STRH W0,[X1]
RET
+ .TEXT
+ .GLOBL outm32
outm32:
STR W0,[X1]
RET
+ .TEXT
+ .GLOBL halt
halt:
MSR DAIFSET,#15
WFE
B halt
-getcontext:
+ .TEXT
+ .GLOBL getctx
+getctx:
STP X0,X1,[X0,#16*0]
STP X2,X3,[X0,#16*1]
STP X4,X5,[X0,#16*2]
@@ -99,7 +118,8 @@ getcontext:
RET
-exception:
+ .TEXT
+EXCEPTION:
MSR SPSEL,#1
STP X0,X1,[SP,#-16*(17-0)]
STP X2,X3,[SP,#-16*(17-1)]
@@ -132,14 +152,15 @@ exception:
MOV X0,SP
MOV X29,#0
BL trap
- ADR X0,outsync
+ ADR X0,OUTSYN
B panic
.DATA
-outsync:
+OUTSYN:
.ASCIZ "out of sync"
.TEXT
+ .GLOBL swtch
swtch:
LDP X9,X10,[X0,#16*17]
MSR FAR_EL1,X10
@@ -171,42 +192,43 @@ swtch:
ERET
.ALIGN 11
+ .GLOBL vectbl
vectbl:
- /* Current EL with SP0 */
- B exception /* Sync */
+// CURRENT EL WITH SP0
+ B EXCEPTION // SYNc
.ALIGN 7
- B exception /* IRQ/vIRQ */
+ B EXCEPTION // IRQ
.ALIGN 7
- B exception /* FIQ/vFIQ */
+ B EXCEPTION // FIQ
.ALIGN 7
- B exception /* SError/VSError */
+ B EXCEPTION // SERROR
- /* Current EL with SPx */
+// CURRENT EL WITH SPX
.ALIGN 7
- B exception /* Sync */
+ B EXCEPTION // SYNC
.ALIGN 7
- B exception /* IRQ/vIRQ */
+ B EXCEPTION // IRQ
.ALIGN 7
- B exception /* FIQ/vFIQ */
+ B EXCEPTION // FIQ
.ALIGN 7
- B exception /* SError/VSError */
+ B EXCEPTION // SERROR
- /* Lower EL using AArch64 */
+// LOWER EL USING AARCH64
.ALIGN 7
- B exception /* Sync */
+ B EXCEPTION // SYNC
.ALIGN 7
- B exception /* IRQ/vIRQ */
+ B EXCEPTION // IRQ
.ALIGN 7
- B exception /* FIQ/vFIQ */
+ B EXCEPTION // FIQ
.ALIGN 7
- B exception /* SError/VSError */
+ B EXCEPTION // SERROR
- /* Lower EL using AArch32 */
+// LOWER EL USING AARCH32
.ALIGN 7
- B exception /* Sync */
+ B EXCEPTION // SYNC
.ALIGN 7
- B exception /* IRQ/vIRQ */
+ B EXCEPTION // IRQ
.ALIGN 7
- B exception /* FIQ/vFIQ */
+ B EXCEPTION // FIQ
.ALIGN 7
- B exception /* SError/VSError */
+ B EXCEPTION // SERROR
diff --git a/src/os9/arch/arm64/main.c b/src/os9/arch/arm64/main.c
@@ -68,7 +68,7 @@ static void
imach(Mach *m)
{
extern void *vectbl;
- unsigned long long tcr, sctlr, ttbr;
+ uint64_t tcr, sctlr, ttbr;
syswr(VBAR_EL1, (phyaddr_t) vectbl);
barrier(ISB);
@@ -161,7 +161,7 @@ main(Mach *m)
imach(m);
halt();
idev();
- intr(IENABLE);
+ interrupt(ENABLE);
barrier(ISB);
namespace();
info();
diff --git a/src/os9/panic.c b/src/os9/panic.c
@@ -83,7 +83,7 @@ panic(const char *msg)
if (first) {
first = 0;
- getcontext(&ctx);
+ getctx(&ctx);
kprint(kerr, "panic: %s\n", msg);
dumpregs(&ctx, kerr);
backtrace(&ctx);
