elfhdr.h (17471B)
1 /* See http://www.sco.com/developers/gabi/latest/contents.html */ 2 3 /* e_ident[] identification indexes */ 4 #define EI_MAG0 0 /* file ID */ 5 #define EI_MAG1 1 /* file ID */ 6 #define EI_MAG2 2 /* file ID */ 7 #define EI_MAG3 3 /* file ID */ 8 #define EI_CLASS 4 /* file class */ 9 #define EI_DATA 5 /* data encoding */ 10 #define EI_VERSION 6 /* ELF header version */ 11 #define EI_OSABI 7 /* OS/ABI ID */ 12 #define EI_ABIVERSION 8 /* ABI version */ 13 #define EI_PAD 9 /* start of pad bytes */ 14 #define EI_NIDENT 16 /* Size of e_ident[] */ 15 16 /* e_ident[] magic number */ 17 #define ELFMAG0 0x7f /* e_ident[EI_MAG0] */ 18 #define ELFMAG1 'E' /* e_ident[EI_MAG1] */ 19 #define ELFMAG2 'L' /* e_ident[EI_MAG2] */ 20 #define ELFMAG3 'F' /* e_ident[EI_MAG3] */ 21 #define ELFMAG "\177ELF" /* magic */ 22 #define SELFMAG 4 /* size of magic */ 23 24 /* e_ident[] file class */ 25 #define ELFCLASSNONE 0 /* invalid */ 26 #define ELFCLASS32 1 /* 32-bit objs */ 27 #define ELFCLASS64 2 /* 64-bit objs */ 28 29 /* e_ident[] data encoding */ 30 #define ELFDATANONE 0 /* invalid */ 31 #define ELFDATA2LSB 1 /* Little-Endian */ 32 #define ELFDATA2MSB 2 /* Big-Endian */ 33 34 /* e_ident[] Operating System/ABI */ 35 #define ELFOSABI_SYSV 0 /* UNIX System V ABI */ 36 #define ELFOSABI_HPUX 1 /* HP-UX operating system */ 37 #define ELFOSABI_NETBSD 2 /* NetBSD */ 38 #define ELFOSABI_LINUX 3 /* GNU/Linux */ 39 #define ELFOSABI_HURD 4 /* GNU/Hurd */ 40 #define ELFOSABI_86OPEN 5 /* 86Open common IA32 ABI */ 41 #define ELFOSABI_SOLARIS 6 /* Solaris */ 42 #define ELFOSABI_MONTEREY 7 /* Monterey */ 43 #define ELFOSABI_IRIX 8 /* IRIX */ 44 #define ELFOSABI_FREEBSD 9 /* FreeBSD */ 45 #define ELFOSABI_TRU64 10 /* TRU64 UNIX */ 46 #define ELFOSABI_MODESTO 11 /* Novell Modesto */ 47 #define ELFOSABI_OPENBSD 12 /* OpenBSD */ 48 #define ELFOSABI_OPENVMS 13 /* Open VMS */ 49 #define ELFOSABI_NSK 14 /* Hewlett-Packard Non-Stop Kernel */ 50 #define ELFOSABI_AROS 15 /* Amiga Research OS */ 51 #define ELFOSABI_FENIXOS 16 /* The FenixOS multi-core OS */ 52 #define ELFOSABI_CLOUDABI 17 /* Nuxi CloudABI */ 53 #define ELFOSABI_OPENVOS 18 /* Stratus Technologies OpenVOS */ 54 #define ELFOSABI_ARM 97 /* ARM */ 55 #define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ 56 57 /* e_ident */ 58 #define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \ 59 (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \ 60 (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \ 61 (ehdr).e_ident[EI_MAG3] == ELFMAG3) 62 63 /* e_machine */ 64 #define EM_NONE 0 /* No machine */ 65 #define EM_M32 1 /* AT&T WE 32100 */ 66 #define EM_SPARC 2 /* SPARC */ 67 #define EM_386 3 /* Intel 80386 */ 68 #define EM_68K 4 /* Motorola 68000 */ 69 #define EM_88K 5 /* Motorola 88000 */ 70 #define EM_IAMCU 6 /* Intel MCU */ 71 #define EM_860 7 /* Intel 80860 */ 72 #define EM_MIPS 8 /* MIPS I Architecture */ 73 #define EM_S370 9 /* IBM System/370 Processor */ 74 #define EM_MIPS_RS3_LE 10 /* MIPS RS3000 Little-endian */ 75 #define EM_PARISC 15 /* Hewlett-Packard PA-RISC */ 76 #define EM_VPP500 17 /* Fujitsu VPP500 */ 77 #define EM_SPARC32PLUS 18 /* Enhanced instruction set SPARC */ 78 #define EM_960 19 /* Intel 80960 */ 79 #define EM_PPC 20 /* PowerPC */ 80 #define EM_PPC64 21 /* 64-bit PowerPC */ 81 #define EM_S390 22 /* IBM System/390 */ 82 #define EM_SPU 23 /* IBM SPU/SPC */ 83 #define EM_V800 36 /* NEC V800 */ 84 #define EM_FR20 37 /* Fujitsu FR20 */ 85 #define EM_RH32 38 /* TRW RH-32 */ 86 #define EM_RCE 39 /* Motorola RCE */ 87 #define EM_ARM 40 /* ARM AARCH32 */ 88 #define EM_ALPHA 41 /* Digital Alpha */ 89 #define EM_SH 42 /* Hitachi SH */ 90 #define EM_SPARCV9 43 /* SPARC Version 9 */ 91 #define EM_TRICORE 44 /* Siemens TriCore */ 92 #define EM_ARC 45 /* Argonaut RISC Core */ 93 #define EM_H8_300 46 /* Hitachi H8/300 */ 94 #define EM_H8_300H 47 /* Hitachi H8/300H */ 95 #define EM_H8S 48 /* Hitachi H8S */ 96 #define EM_H8_500 49 /* Hitachi H8/500 */ 97 #define EM_IA_64 50 /* Intel IA-64 */ 98 #define EM_MIPS_X 51 /* Stanford MIPS-X */ 99 #define EM_COLDFIRE 52 /* Motorola ColdFire */ 100 #define EM_68HC12 53 /* Motorola M68HC12 */ 101 #define EM_MMA 54 /* Fujitsu MMA */ 102 #define EM_PCP 55 /* Siemens PCP */ 103 #define EM_NCPU 56 /* Sony nCPU */ 104 #define EM_NDR1 57 /* Denso NDR1 */ 105 #define EM_STARCORE 58 /* Motorola Star*Core */ 106 #define EM_ME16 59 /* Toyota ME16 */ 107 #define EM_ST100 60 /* STMicroelectronics ST100 */ 108 #define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ */ 109 #define EM_X86_64 62 /* AMD x86-64 */ 110 #define EM_PDSP 63 /* Sony DSP Processor */ 111 #define EM_PDP10 64 /* DEC PDP-10 */ 112 #define EM_PDP11 65 /* DEC PDP-11 */ 113 #define EM_FX66 66 /* Siemens FX66 */ 114 #define EM_ST9PLUS 67 /* STMicroelectronics ST9+ */ 115 #define EM_ST7 68 /* STMicroelectronics ST7 */ 116 #define EM_68HC16 69 /* Motorola MC68HC16 */ 117 #define EM_68HC11 70 /* Motorola MC68HC11 */ 118 #define EM_68HC08 71 /* Motorola MC68HC08 */ 119 #define EM_68HC05 72 /* Motorola MC68HC05 */ 120 #define EM_SVX 73 /* Silicon Graphics SVx */ 121 #define EM_ST19 74 /* STMicroelectronics ST19 */ 122 #define EM_VAX 75 /* Digital VAX */ 123 #define EM_CRIS 76 /* Axis Communications 32-bit */ 124 #define EM_JAVELIN 77 /* Infineon Technologies 32-bit */ 125 #define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ 126 #define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ 127 #define EM_MMIX 80 /* Donald Knuth's educational 64-bit */ 128 #define EM_HUANY 81 /* Harvard machine-independent */ 129 #define EM_PRISM 82 /* SiTera Prism */ 130 #define EM_AVR 83 /* Atmel AVR 8-bit */ 131 #define EM_FR30 84 /* Fujitsu FR30 */ 132 #define EM_D10V 85 /* Mitsubishi D10V */ 133 #define EM_D30V 86 /* Mitsubishi D30V */ 134 #define EM_V850 87 /* NEC v850 */ 135 #define EM_M32R 88 /* Mitsubishi M32R */ 136 #define EM_MN10300 89 /* Matsushita MN10300 */ 137 #define EM_MN10200 90 /* Matsushita MN10200 */ 138 #define EM_PJ 91 /* picoJava */ 139 #define EM_OPENRISC 92 /* OpenRISC 32-bit */ 140 #define EM_ARC_A5 93 /* ARC ARCompact */ 141 #define EM_ARC_COMPACT 93 /* ARC ARCompact */ 142 #define EM_XTENSA 94 /* Tensilica Xtensa */ 143 #define EM_VIDEOCORE 95 /* Alphamosaic VideoCore */ 144 #define EM_TMM_GPP 96 /* Thompson Multimedia GPP */ 145 #define EM_NS32K 97 /* National 32000 series */ 146 #define EM_TPC 98 /* Tenor Network TPC */ 147 #define EM_SNP1K 99 /* Trebia SNP 1000 */ 148 #define EM_ST200 100 /* STMicroelectronics ST200 */ 149 #define EM_IP2K 101 /* Ubicom IP2xxx */ 150 #define EM_MAX 102 /* MAX Processor */ 151 #define EM_CR 103 /* National CompactRISC */ 152 #define EM_F2MC16 104 /* Fujitsu F2MC16 */ 153 #define EM_MSP430 105 /* Texas msp430 */ 154 #define EM_BLACKFIN 106 /* Analog Devices Blackfin */ 155 #define EM_SE_C33 107 /* S1C33 of Seiko Epson */ 156 #define EM_SEP 108 /* Sharp embedded */ 157 #define EM_ARCA 109 /* Arca RISC */ 158 #define EM_UNICORE 110 /* PKU-Unity Ltd. and MPRC */ 159 #define EM_EXCESS 111 /* eXcess CPU */ 160 #define EM_DXP 112 /* Deep Execution Processor */ 161 #define EM_ALTERA_NIOS2 113 /* Altera Nios II */ 162 #define EM_CRX 114 /* National CompactRISC CRX */ 163 #define EM_XGATE 115 /* Motorola XGATE */ 164 #define EM_C166 116 /* Infineon C16x/XC16x */ 165 #define EM_M16C 117 /* Renesas M16C */ 166 #define EM_DSPIC30F 118 /* Microchip dsPIC30F */ 167 #define EM_CE 119 /* Freescale Communication Engine */ 168 #define EM_M32C 120 /* Renesas M32C */ 169 #define EM_TSK3000 131 /* Altium TSK3000 core */ 170 #define EM_RS08 132 /* Freescale RS08 */ 171 #define EM_SHARC 133 /* Analog Devices SHARC */ 172 #define EM_ECOG2 134 /* Cyan Technology eCOG2 */ 173 #define EM_SCORE7 135 /* Sunplus S+core7 */ 174 #define EM_DSP24 136 /* NJR 24-bit DSP */ 175 #define EM_VIDEOCORE3 137 /* Broadcom VideoCore III */ 176 #define EM_LATTICEMICO3 138 /* RISC processor for Lattice FPGA */ 177 #define EM_SE_C17 139 /* Seiko Epson C17 */ 178 #define EM_TI_C6000 140 /* TMS320C6000 DSP family */ 179 #define EM_TI_C2000 141 /* TMS320C2000 DSP family */ 180 #define EM_TI_C5500 142 /* TMS320C55x DSP family */ 181 #define EM_TI_ARP32 143 /* Texas Application Specific RISC */ 182 #define EM_TI_PRU 144 /* Texas Programmable Realtime Unit */ 183 #define EM_MMDSP_PLUS 160 /* STMicroelectronics 64bit VLIW */ 184 #define EM_CYPRESS_M8C 161 /* Cypress M8C microprocessor */ 185 #define EM_R32C 162 /* Renesas R32C series */ 186 #define EM_TRIMEDIA 163 /* NXP Semiconductors TriMedia */ 187 #define EM_QDSP6 164 /* QUALCOMM DSP6 Processor */ 188 #define EM_8051 165 /* Intel 8051 and variants */ 189 #define EM_STXP7X 166 /* STMicroelectronics STxP7x */ 190 #define EM_NDS32 167 /* Andes Technology embedded RISC */ 191 #define EM_ECOG1 168 /* Cyan Technology eCOG1X family */ 192 #define EM_ECOG1X 168 /* Cyan Technology eCOG1X family */ 193 #define EM_MAXQ30 169 /* MAXQ30 Core Micro-controllers */ 194 #define EM_XIMO16 170 /* NJR 16-bit DSP Processor */ 195 #define EM_MANIK 171 /* M2000 Reconfigurable RISC */ 196 #define EM_CRAYNV2 172 /* Cray Inc. NV2 vector architecture */ 197 #define EM_RX 173 /* Renesas RX family */ 198 #define EM_METAG 174 /* Imagination Technologies META */ 199 #define EM_MCST_ELBRUS 175 /* MCST Elbrus */ 200 #define EM_ECOG16 176 /* Cyan Technology eCOG16 family */ 201 #define EM_CR16 177 /* National CompactRISC CR16 */ 202 #define EM_ETPU 178 /* Freescale Extended Time Unit */ 203 #define EM_SLE9X 179 /* Infineon Technologies SLE9X core */ 204 #define EM_L10M 180 /* Intel L10M */ 205 #define EM_K10M 181 /* Intel K10M */ 206 #define EM_AARCH64 183 /* ARM AARCH64 */ 207 #define EM_AVR32 185 /* Atmel 32-bit */ 208 #define EM_STM8 186 /* STMicroeletronics STM8 */ 209 #define EM_TILE64 187 /* Tilera TILE64 */ 210 #define EM_TILEPRO 188 /* Tilera TILEPro */ 211 #define EM_MICROBLAZE 189 /* Xilinx MicroBlaze 32-bit */ 212 #define EM_CUDA 190 /* NVIDIA CUDA architecture */ 213 #define EM_TILEGX 191 /* Tilera TILE-Gx family */ 214 #define EM_CLOUDSHIELD 192 /* CloudShield architecture family */ 215 #define EM_COREA_1ST 193 /* KIPO-KAIST Core-A 1st gen family */ 216 #define EM_COREA_2ND 194 /* KIPO-KAIST Core-A 2nd gen family */ 217 #define EM_ARC_COMPACT2 195 /* Synopsys ARCompact V2 */ 218 #define EM_OPEN8 196 /* Open8 8-bit RISC soft processor core */ 219 #define EM_RL78 197 /* Renesas RL78 family */ 220 #define EM_VIDEOCORE5 198 /* Broadcom VideoCore V processor */ 221 #define EM_78KOR 199 /* Renesas 78KOR family */ 222 #define EM_56800EX 200 /* Freescale 56800EX (DSC) */ 223 #define EM_BA1 201 /* Beyond BA1 CPU architecture */ 224 #define EM_BA2 202 /* Beyond BA2 CPU architecture */ 225 #define EM_XCORE 203 /* XMOS xCORE processor family */ 226 #define EM_MCHP_PIC 204 /* Microchip 8-bit PIC(r) family */ 227 #define EM_KM32 210 /* KM211 KM32 32-bit processor */ 228 #define EM_KMX32 211 /* KM211 KMX32 32-bit processor */ 229 #define EM_KMX16 212 /* KM211 KMX16 16-bit processor */ 230 #define EM_KMX8 213 /* KM211 KMX8 8-bit processor */ 231 #define EM_KVARC 214 /* KM211 KVARC processor */ 232 #define EM_CDP 215 /* Paneve CDP architecture family */ 233 #define EM_COGE 216 /* Cognitive Smart Memory Processor */ 234 #define EM_COOL 217 /* Bluechip Systems CoolEngine */ 235 #define EM_NORC 218 /* Nanoradio Optimized RISC */ 236 #define EM_CSR_KALIMBA 219 /* CSR Kalimba architecture family */ 237 #define EM_Z80 220 /* Zilog Z80 */ 238 #define EM_VISIUM 221 /* VISIUMcore processor */ 239 #define EM_FT32 222 /* FTDI Chip FT32 */ 240 #define EM_MOXIE 223 /* Moxie processor family */ 241 #define EM_AMDGPU 224 /* AMD GPU architecture */ 242 #define EM_RISCV 243 /* RISC-V */ 243 #define EM_BPF 247 /* Linux BPF */ 244 #define EM_CSKY 252 /* C-SKY */ 245 246 /* e_type */ 247 #define ET_NONE 0 /* No file type */ 248 #define ET_REL 1 /* Relocatable file */ 249 #define ET_EXEC 2 /* Executable file */ 250 #define ET_DYN 3 /* Shared object file */ 251 #define ET_CORE 4 /* Core file */ 252 #define ET_LOOS 0xfe00 /* Operating system-specific */ 253 #define ET_HIOS 0xfeff /* Operating system-specific */ 254 #define ET_LOPROC 0xff00 /* Processor-specific */ 255 #define ET_HIPROC 0xffff /* Processor-specific */ 256 257 /* Version */ 258 #define EV_NONE 0 /* Invalid */ 259 #define EV_CURRENT 1 /* Current */ 260 261 /* Magic for e_phnum: get real value from sh_info of first section header */ 262 #define PN_XNUM 0xffff 263 264 #define ELFH32SZ 54 265 #define ELFH64SZ 64 266 267 typedef struct elfhdr32 Elf32_Ehdr; 268 typedef struct elfhdr64 Elf64_Ehdr; 269 270 struct elfhdr32 { 271 unsigned char e_ident[EI_NIDENT];/* ELF Identification */ 272 Elf32_Half e_type; /* object file type */ 273 Elf32_Half e_machine; /* machine */ 274 Elf32_Word e_version; /* object file version */ 275 Elf32_Addr e_entry; /* virtual entry point */ 276 Elf32_Off e_phoff; /* program header table offset */ 277 Elf32_Off e_shoff; /* section header table offset */ 278 Elf32_Word e_flags; /* processor-specific flags */ 279 Elf32_Half e_ehsize; /* ELF header size */ 280 Elf32_Half e_phentsize; /* program header entry size */ 281 Elf32_Half e_phnum; /* number of program header entries */ 282 Elf32_Half e_shentsize; /* section header entry size */ 283 Elf32_Half e_shnum; /* number of section header entries */ 284 Elf32_Half e_shstrndx; /* section header table's "section 285 header string table" entry offset */ 286 }; 287 288 struct elfhdr64 { 289 unsigned char e_ident[EI_NIDENT];/* Id bytes */ 290 Elf64_Half e_type; /* file type */ 291 Elf64_Half e_machine; /* machine type */ 292 Elf64_Word e_version; /* version number */ 293 Elf64_Addr e_entry; /* entry point */ 294 Elf64_Off e_phoff; /* Program hdr offset */ 295 Elf64_Off e_shoff; /* Section hdr offset */ 296 Elf64_Word e_flags; /* Processor flags */ 297 Elf64_Half e_ehsize; /* sizeof ehdr */ 298 Elf64_Half e_phentsize; /* Program header entry size */ 299 Elf64_Half e_phnum; /* Number of program headers */ 300 Elf64_Half e_shentsize; /* Section header entry size */ 301 Elf64_Half e_shnum; /* Number of section headers */ 302 Elf64_Half e_shstrndx; /* String table index */ 303 };