scc

simple c99 compiler
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commit e082f4ab7ab853d303e2b6cd329aabbfb0493b1a
parent 0dc11ffd0af669fcb98ba8412d2a089d410314d5
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Sun, 17 Dec 2017 19:50:23 +0100

[as-z80] Add index load operations

Diffstat:
Mas/target/gen.awk | 6+++++-
Mas/target/x80/ins.c | 23+++++++++++++++++++++++
Mas/target/x80/proc.h | 3+++
Mas/target/x80/x80.dat | 6++++++
Mas/target/z80/proc.c | 11+++++++++++
5 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/as/target/gen.awk b/as/target/gen.awk @@ -74,7 +74,11 @@ function str2args(s, args, i, out, n) } else if (match(a, /^imm32/)) { out = out "AIMM32" } else if (match(a, /^imm64/)) { - out = "AIMM64" + out = out "AIMM64" + } else if (match(a, /^idx_IY/)) { + out = out "AINDEX_IY" + } else if (match(a, /^idx_IX/)) { + out = out "AINDEX_IX" } else if (match(a, /^reg_dd/)) { out = out "AREG_DDCLASS" } else if (match(a, /^reg_qq/)) { diff --git a/as/target/x80/ins.c b/as/target/x80/ins.c @@ -129,6 +129,29 @@ r8_imm8(Op *op, Node **args) } void +r8_idx(Op *op, Node **args) +{ + args[1] = args[1]->left; + r8_imm8(op, args); +} + +void +idx_r8(Op *op, Node **args) +{ + Node *par1, *par2; + unsigned char buf[3]; + int n = op->size; + + par1 = args[0]->left; + par2 = args[1]; + + memcpy(buf, op->bytes, n-1); + buf[n-1] = par1->sym->value; + buf[n-2] |= reg2int(par2->sym->argtype); + emit(buf, n); +} + +void imm8(Op *op, Node **args) { Node *par1, *par2; diff --git a/as/target/x80/proc.h b/as/target/x80/proc.h @@ -35,6 +35,9 @@ enum args { AREG_DDCLASS, /* register class for BC, DE, HL and SP */ AREG_QQCLASS, /* register class for BC, DE, HL and AF */ + AINDEX_IX, + AINDEX_IY, + AINDER_HL, /* (HL) */ }; diff --git a/as/target/x80/x80.dat b/as/target/x80/x80.dat @@ -77,6 +77,7 @@ OTDR none 2 0xed,0xbb noargs Z80,R800 # dd is any register from BC, DE, HL, SP # qq is any register from BC, DE, HL, AF +# 8 bit load group LD reg_r,imm8 2 0x06 r8_imm8 Z80,R800,GB80 LD reg_p,imm8 3 0xdd,0x06 r8_imm8 Z80,R800 LD reg_q,imm8 3 0xfd,0x06 r8_imm8 Z80,R800 @@ -88,6 +89,11 @@ LD reg_q,reg_q 2 0xfd,0x40 r8_r8 Z80,R800 LD indir_HL,reg_r 1 0x70 xx_r8 Z80,R800,GB80 LD reg_r,indir_HL 1 0x46 r8_xx Z80,R800,GB80 +LD reg_r,idx_IX 3 0xdd,0x46 r8_idx Z80,R800 +LD reg_r,idx_IY 3 0xfd,0x46 r8_idx Z80,R800 +LD idx_IX,reg_r 3 0xdd,0x70 idx_r8 Z80,R800 +LD idx_IY,reg_r 3 0xfd,0x70 idx_r8 Z80,R800 + # 16 bit load group LD reg_dd,imm16 3 0x01 r16_imm16 Z80,R800,GB80 LD regIX,imm16 4 0xdd,0x21 imm16 Z80,R800 diff --git a/as/target/z80/proc.c b/as/target/z80/proc.c @@ -104,6 +104,17 @@ match(Op *op, Node **args) if (!(*class)(np->sym->argtype)) return 0; break; + case AINDEX_IY: + arg = AREG_IY; + goto index_address; + case AINDEX_IX: + arg = AREG_IX; + index_address: + if (np->addr != AINDEX) + return 0; + if (np->left->left->sym->argtype != arg) + return 0; + break; case AIMM8: case AIMM16: case AIMM32: