scc

simple c99 compiler
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commit a55afedf4d36c77c64456f92620d9ab576603fb1
parent 38df2f7d8bbde9f7d5083da7f22734e3c4836f27
Author: Roberto E. Vargas Caballero <k0ga@shike2.com>
Date:   Thu, 28 Dec 2017 11:40:39 +0000

[as-z80] Add test for indexed instructions

Diffstat:
Mas/target/x80/ins.c | 104++++++++++++++++++++++++++++++++++++++++++++++---------------------------------
Mas/target/x80/x80.dat | 198++++++++++++++++++++++++++++++++++++++++----------------------------------------
Mas/target/z80/test.s | 100++++++++++++++++++++++++++++++++++++++++----------------------------------------
3 files changed, 210 insertions(+), 192 deletions(-)

diff --git a/as/target/x80/ins.c b/as/target/x80/ins.c @@ -191,45 +191,6 @@ r8_imm8(Op *op, Node **args) } void -r8_idx(Op *op, Node **args) -{ - args[1] = args[1]->left; - r8_imm8(op, args); -} - -void -idx_r8(Op *op, Node **args) -{ - Node *par1, *par2; - unsigned char buf[3]; - int n = op->size; - - par1 = args[0]->left; - par2 = args[1]; - - memcpy(buf, op->bytes, n); - buf[n-1] = par1->sym->value; - buf[n-2] |= reg2int(par2->sym->argtype); - emit(buf, n); -} - -void -idx_imm8(Op *op, Node **args) -{ - Node *par1, *par2; - unsigned char buf[3]; - int n = op->size; - - par1 = args[0]->left; - par2 = args[1]; - - memcpy(buf, op->bytes, n); - buf[n-1] = par1->sym->value; - buf[n-2] = par2->sym->value; - emit(buf, n); -} - -void imm8(Op *op, Node **args) { Node *par1, *par2; @@ -372,15 +333,72 @@ r16_dir(Op *op, Node **args) } void +alu(Op *op, Node **args) +{ + Node *par = args[1]; + unsigned char buf[4], val; + int n = op->size, shift; + + if (args[1]) { + shift = 0; + par = args[1]; + } else { + shift = 3; + par = args[0]; + } + + switch (par->addr) { + case AIMM: + val = par->sym->value; + break; + case AREG: + val = reg2int(par->sym->argtype) << shift; + break; + case AINDEX: + val = par->left->right->sym->value; + break; + case AINDIR: + val = 0; + break; + default: + abort(); + } + + memcpy(buf, op->bytes, n); + buf[n-1] |= val; + emit(buf, n); +} + +void idx(Op *op, Node **args) { - Node *imm; + Node *tmp, *idx, *imm, *reg; unsigned char buf[4]; - int n = op->size; + int n = op->size, i = n, shift = 0; + + imm = reg = NULL; + if (args[0]->addr != AINDEX) { + shift = 3; + tmp = args[0]; + args[0] = args[1]; + args[1] = tmp; + } + idx = args[0]->left->right; - imm = args[0]->left->right; + if (args[1]) { + if (args[1]->addr == AREG) + reg = args[1]; + else + imm = args[1]; + } memcpy(buf, op->bytes, n); - buf[n-1] = imm->sym->value; + + if (imm) + buf[--i] = imm->sym->value; + buf[--i] = idx->sym->value; + if (reg) + buf[--i] |= reg2int(reg->sym->argtype) << shift; + emit(buf, n); } diff --git a/as/target/x80/x80.dat b/as/target/x80/x80.dat @@ -57,14 +57,14 @@ LD q,q 2 0xfd,0x40 r8_r8 Z80,R800 LD (HL),r 1 0x70 xx_r8 Z80,R800,GB80 LD r,(HL) 1 0x46 r8_xx Z80,R800,GB80 -LD r,(IX+n) 3 0xdd,0x46 r8_idx Z80,R800 -LD r,(IY+n) 3 0xfd,0x46 r8_idx Z80,R800 -LD (IX+n),r 3 0xdd,0x70 idx_r8 Z80,R800 -LD (IY+n),r 3 0xfd,0x70 idx_r8 Z80,R800 +LD r,(IX+n) 3 0xdd,0x46 idx Z80,R800 +LD r,(IY+n) 3 0xfd,0x46 idx Z80,R800 +LD (IX+n),r 3 0xdd,0x70 idx Z80,R800 +LD (IY+n),r 3 0xfd,0x70 idx Z80,R800 LD (HL),imm8 2 0x36 imm8 Z80,R800,GB80 -LD (IX+n),imm8 3 0xdd,0x36 idx_imm8 Z80,R800 -LD (IY+n),imm8 3 0xfd,0x36 idx_imm8 Z80,R800 +LD (IX+n),imm8 4 0xdd,0x36 idx Z80,R800 +LD (IY+n),imm8 4 0xfd,0x36 idx Z80,R800 LD A,(BC) 1 0x0a noargs Z80,R800,GB80 LD A,(DE) 1 0x1a noargs Z80,R800,GB80 @@ -106,83 +106,83 @@ POP IX 2 0xdd,0xe1 noargs Z80,R800 POP IY 2 0xfd,0xe1 noargs Z80,R800 # 8 bit ALU group -ADD A,r 1 0x80 xx_r8 Z80,R800,GB80 -ADD A,p 2 0xdd,0x80 xx_r8 Z80,R800 -ADD A,q 2 0xfd,0x80 xx_r8 Z80,R800 -ADD A,imm8 2 0xc6 imm8 Z80,R800,GB80 -ADD A,(HL) 1 0x86 noargs Z80,R800,GB80 -ADD A,(IX+n) 3 0xdd,0x86 idx Z80,R800 -ADD A,(IY+n) 3 0xfd,0x86 idx Z80,R800 - -ADC A,r 1 0x88 xx_r8 Z80,R800,GB80 -ADC A,p 2 0xdd,0x88 xx_r8 Z80,R800 -ADC A,q 2 0xfd,0x88 xx_r8 Z80,R800 -ADC A,imm8 2 0xce imm8 Z80,R800,GB80 -ADC A,(HL) 1 0x8e noargs Z80,R800,GB80 -ADC A,(IX+n) 3 0xdd,0x8e idx Z80,R800 -ADC A,(IY+n) 3 0xfd,0x8e idx Z80,R800 - -SUB A,r 1 0x90 xx_r8 Z80,R800,GB80 -SUB A,p 2 0xdd,0x90 xx_r8 Z80,R800 -SUB A,q 2 0xfd,0x90 xx_r8 Z80,R800 -SUB A,imm8 2 0xd6 imm8 Z80,R800,GB80 -SUB A,(HL) 1 0x96 noargs Z80,R800,GB80 -SUB A,(IX+n) 3 0xdd,0x96 idx Z80,R800 -SUB A,(IY+n) 3 0xfd,0x96 idx Z80,R800 - -SBC A,r 1 0x98 xx_r8 Z80,R800,GB80 -SBC A,p 2 0xdd,0x98 xx_r8 Z80,R800 -SBC A,q 2 0xfd,0x98 xx_r8 Z80,R800 -SBC A,imm8 2 0xde imm8 Z80,R800,GB80 -SBC A,(HL) 1 0x9e noargs Z80,R800,GB80 -SBC A,(IX+n) 3 0xdd,0x9e idx Z80,R800 -SBC A,(IY+n) 3 0xfd,0x9e idx Z80,R800 - -AND A,r 1 0xa0 xx_r8 Z80,R800,GB80 -AND A,p 2 0xdd,0xa0 xx_r8 Z80,R800 -AND A,q 2 0xfd,0xa0 xx_r8 Z80,R800 -AND A,imm8 2 0xe6 imm8 Z80,R800,GB80 -AND A,(HL) 1 0xa6 noargs Z80,R800,GB80 -AND A,(IX+n) 3 0xdd,0xa6 idx Z80,R800 -AND A,(IY+n) 3 0xfd,0xa6 idx Z80,R800 - -OR A,r 1 0xb0 xx_r8 Z80,R800,GB80 -OR A,p 2 0xdd,0xb0 xx_r8 Z80,R800 -OR A,q 2 0xfd,0xb0 xx_r8 Z80,R800 -OR A,imm8 2 0xf6 imm8 Z80,R800,GB80 -OR A,(HL) 1 0xb6 noargs Z80,R800,GB80 -OR A,(IX+n) 3 0xdd,0xb6 idx Z80,R800 -OR A,(IY+n) 3 0xfd,0xb6 idx Z80,R800 - -XOR A,r 1 0xa8 xx_r8 Z80,R800,GB80 -XOR A,p 2 0xdd,0xa8 xx_r8 Z80,R800 -XOR A,q 2 0xfd,0xa8 xx_r8 Z80,R800 -XOR A,imm8 2 0xee imm8 Z80,R800,GB80 -XOR A,(HL) 1 0xae noargs Z80,R800,GB80 -XOR A,(IX+n) 3 0xdd,0xa6 idx Z80,R800 -XOR A,(IY+n) 3 0xfd,0xa6 idx Z80,R800 - -CP A,r 1 0xb8 xx_r8 Z80,R800,GB80 -CP A,p 2 0xdd,0xb8 xx_r8 Z80,R800 -CP A,q 2 0xfd,0xb8 xx_r8 Z80,R800 -CP A,imm8 2 0xfe imm8 Z80,R800,GB80 -CP A,(HL) 1 0xbe noargs Z80,R800,GB80 -CP A,(IX+n) 3 0xdd,0xbe idx Z80,R800 -CP A,(IY+n) 3 0xfd,0xbe idx Z80,R800 - -INC r 1 0x04 r8_xx Z80,R800,GB80 -INC p 2 0xdd,0x04 r8_xx Z80,R800 -INC q 2 0xfd,0x04 r8_xx Z80,R800 -INC (HL) 1 0x34 noargs Z80,R800,GB80 -INC (IX+n) 3 0xdd,0x34 idx Z80,R800 -INC (IY+n) 3 0xfd,0x34 idx Z80,R800 - -DEC r 1 0x05 r8_xx Z80,R800,GB80 -DEC p 2 0xdd,0x05 r8_xx Z80,R800 -DEC q 2 0xfd,0x05 r8_xx Z80,R800 -DEC (HL) 1 0x35 noargs Z80,R800,GB80 -DEC (IX+n) 3 0xdd,0x35 idx Z80,R800 -DEC (IY+n) 3 0xfd,0x35 idx Z80,R800 +ADD A,r 1 0x80 alu Z80,R800,GB80 +ADD A,p 2 0xdd,0x80 alu Z80,R800 +ADD A,q 2 0xfd,0x80 alu Z80,R800 +ADD A,imm8 2 0xc6 alu Z80,R800,GB80 +ADD A,(HL) 1 0x86 alu Z80,R800,GB80 +ADD A,(IX+n) 3 0xdd,0x86 alu Z80,R800 +ADD A,(IY+n) 3 0xfd,0x86 alu Z80,R800 + +ADC A,r 1 0x88 alu Z80,R800,GB80 +ADC A,p 2 0xdd,0x88 alu Z80,R800 +ADC A,q 2 0xfd,0x88 alu Z80,R800 +ADC A,imm8 2 0xce alu Z80,R800,GB80 +ADC A,(HL) 1 0x8e alu Z80,R800,GB80 +ADC A,(IX+n) 3 0xdd,0x8e alu Z80,R800 +ADC A,(IY+n) 3 0xfd,0x8e alu Z80,R800 + +SUB A,r 1 0x90 alu Z80,R800,GB80 +SUB A,p 2 0xdd,0x90 alu Z80,R800 +SUB A,q 2 0xfd,0x90 alu Z80,R800 +SUB A,imm8 2 0xd6 alu Z80,R800,GB80 +SUB A,(HL) 1 0x96 alu Z80,R800,GB80 +SUB A,(IX+n) 3 0xdd,0x96 alu Z80,R800 +SUB A,(IY+n) 3 0xfd,0x96 alu Z80,R800 + +SBC A,r 1 0x98 alu Z80,R800,GB80 +SBC A,p 2 0xdd,0x98 alu Z80,R800 +SBC A,q 2 0xfd,0x98 alu Z80,R800 +SBC A,imm8 2 0xde alu Z80,R800,GB80 +SBC A,(HL) 1 0x9e alu Z80,R800,GB80 +SBC A,(IX+n) 3 0xdd,0x9e alu Z80,R800 +SBC A,(IY+n) 3 0xfd,0x9e alu Z80,R800 + +AND A,r 1 0xa0 alu Z80,R800,GB80 +AND A,p 2 0xdd,0xa0 alu Z80,R800 +AND A,q 2 0xfd,0xa0 alu Z80,R800 +AND A,imm8 2 0xe6 alu Z80,R800,GB80 +AND A,(HL) 1 0xa6 alu Z80,R800,GB80 +AND A,(IX+n) 3 0xdd,0xa6 alu Z80,R800 +AND A,(IY+n) 3 0xfd,0xa6 alu Z80,R800 + +OR A,r 1 0xb0 alu Z80,R800,GB80 +OR A,p 2 0xdd,0xb0 alu Z80,R800 +OR A,q 2 0xfd,0xb0 alu Z80,R800 +OR A,imm8 2 0xf6 alu Z80,R800,GB80 +OR A,(HL) 1 0xb6 alu Z80,R800,GB80 +OR A,(IX+n) 3 0xdd,0xb6 alu Z80,R800 +OR A,(IY+n) 3 0xfd,0xb6 alu Z80,R800 + +XOR A,r 1 0xa8 alu Z80,R800,GB80 +XOR A,p 2 0xdd,0xa8 alu Z80,R800 +XOR A,q 2 0xfd,0xa8 alu Z80,R800 +XOR A,imm8 2 0xee alu Z80,R800,GB80 +XOR A,(HL) 1 0xae alu Z80,R800,GB80 +XOR A,(IX+n) 3 0xdd,0xae alu Z80,R800 +XOR A,(IY+n) 3 0xfd,0xae alu Z80,R800 + +CP A,r 1 0xb8 alu Z80,R800,GB80 +CP A,p 2 0xdd,0xb8 alu Z80,R800 +CP A,q 2 0xfd,0xb8 alu Z80,R800 +CP A,imm8 2 0xfe alu Z80,R800,GB80 +CP A,(HL) 1 0xbe alu Z80,R800,GB80 +CP A,(IX+n) 3 0xdd,0xbe alu Z80,R800 +CP A,(IY+n) 3 0xfd,0xbe alu Z80,R800 + +INC r 1 0x04 alu Z80,R800,GB80 +INC p 2 0xdd,0x04 alu Z80,R800 +INC q 2 0xfd,0x04 alu Z80,R800 +INC (HL) 1 0x34 alu Z80,R800,GB80 +INC (IX+n) 3 0xdd,0x34 alu Z80,R800 +INC (IY+n) 3 0xfd,0x34 alu Z80,R800 + +DEC r 1 0x05 alu Z80,R800,GB80 +DEC p 2 0xdd,0x05 alu Z80,R800 +DEC q 2 0xfd,0x05 alu Z80,R800 +DEC (HL) 1 0x35 alu Z80,R800,GB80 +DEC (IX+n) 3 0xdd,0x35 alu Z80,R800 +DEC (IY+n) 3 0xfd,0x35 alu Z80,R800 # 16 bit ALU group ADD HL,dd 1 0x09 xx_r16 Z80,R800,GB80 @@ -242,57 +242,57 @@ RLC r 2 0xcb,0x00 r8 Z80,R800 RLC (HL) 2 0xcb,0x06 noargs Z80,R800 RLC (IX+n) 4 0xdd,0xcb,0x06 idx Z80,R800 RLC (IY+n) 4 0xfd,0xcb,0x06 idx Z80,R800 -RLC (IX+n),r 4 0xdd,0xcb,0,0x00 idx_r8 Z80,R800 -RLC (IY+n),r 4 0xfd,0xcb,0,0x00 idx_r8 Z80,R800 +RLC (IX+n),r 4 0xdd,0xcb,0,0x00 idx Z80,R800 +RLC (IY+n),r 4 0xfd,0xcb,0,0x00 idx Z80,R800 RL r 2 0xcb,0x10 r8 Z80,R800 RL (HL) 2 0xcb,0x16 noargs Z80,R800 RL (IX+n) 4 0xdd,0xcb,0x16 idx Z80,R800 RL (IY+n) 4 0xfd,0xcb,0x16 idx Z80,R800 -RL (IX+n),r 4 0xdd,0xcb,0,0x10 idx_r8 Z80,R800 -RL (IY+n),r 4 0xfd,0xcb,0,0x10 idx_r8 Z80,R800 +RL (IX+n),r 4 0xdd,0xcb,0,0x10 idx Z80,R800 +RL (IY+n),r 4 0xfd,0xcb,0,0x10 idx Z80,R800 RRC r 2 0xcb,0x08 r8 Z80,R800 RRC (HL) 2 0xcb,0x0e noargs Z80,R800 RRC (IX+n) 4 0xdd,0xcb,0x06 idx Z80,R800 RRC (IY+n) 4 0xfd,0xcb,0x06 idx Z80,R800 -RRC (IX+n),r 4 0xdd,0xcb,0,0x08 idx_r8 Z80,R800 -RRC (IY+n),r 4 0xfd,0xcb,0,0x08 idx_r8 Z80,R800 +RRC (IX+n),r 4 0xdd,0xcb,0,0x08 idx Z80,R800 +RRC (IY+n),r 4 0xfd,0xcb,0,0x08 idx Z80,R800 RR r 2 0xcb,0x18 r8 Z80,R800 RR (HL) 2 0xcb,0x1e noargs Z80,R800 RR (IX+n) 4 0xdd,0xcb,0x1e idx Z80,R800 RR (IY+n) 4 0xfd,0xcb,0x1e idx Z80,R800 -RR (IX+n),r 4 0xdd,0xcb,0,0x18 idx_r8 Z80,R800 -RR (IY+n),r 4 0xfd,0xcb,0,0x18 idx_r8 Z80,R800 +RR (IX+n),r 4 0xdd,0xcb,0,0x18 idx Z80,R800 +RR (IY+n),r 4 0xfd,0xcb,0,0x18 idx Z80,R800 SLA r 2 0xcb,0x20 r8 Z80,R800 SLA (HL) 2 0xcb,0x26 noargs Z80,R800 SLA (IX+n) 4 0xdd,0xcb,0x26 idx Z80,R800 SLA (IY+n) 4 0xfd,0xcb,0x26 idx Z80,R800 -SLA (IX+n),r 4 0xdd,0xcb,0,0x20 idx_r8 Z80,R800 -SLA (IY+n),r 4 0xfd,0xcb,0,0x20 idx_r8 Z80,R800 +SLA (IX+n),r 4 0xdd,0xcb,0,0x20 idx Z80,R800 +SLA (IY+n),r 4 0xfd,0xcb,0,0x20 idx Z80,R800 SLL r 2 0xcb,0x30 r8 Z80 SLL (HL) 2 0xcb,0x36 noargs Z80 SLL (IX+n) 4 0xdd,0xcb,0x36 idx Z80 SLL (IY+n) 4 0xfd,0xcb,0x36 idx Z80 -SLL (IX+n),r 4 0xdd,0xcb,0,0x30 idx_r8 Z80 -SLL (IY+n),r 4 0xfd,0xcb,0,0x30 idx_r8 Z80 +SLL (IX+n),r 4 0xdd,0xcb,0,0x30 idx Z80 +SLL (IY+n),r 4 0xfd,0xcb,0,0x30 idx Z80 SRA r 2 0xcb,0x28 r8 Z80,R800 SRA (HL) 2 0xcb,0x2e noargs Z80,R800 SRA (IX+n) 4 0xdd,0xcb,0x2e idx Z80,R800 SRA (IY+n) 4 0xfd,0xcb,0x2e idx Z80,R800 -SRA (IX+n),r 4 0xdd,0xcb,0,0x28 idx_r8 Z80,R800 -SRA (IY+n),r 4 0xfd,0xcb,0,0x28 idx_r8 Z80,R800 +SRA (IX+n),r 4 0xdd,0xcb,0,0x28 idx Z80,R800 +SRA (IY+n),r 4 0xfd,0xcb,0,0x28 idx Z80,R800 SRL r 2 0xcb,0x38 r8 Z80,R800 SRL (HL) 2 0xcb,0x3e noargs Z80,R800 SRL (IX+n) 4 0xdd,0xcb,0x3e idx Z80,R800 SRL (IY+n) 4 0xfd,0xcb,0x3e idx Z80,R800 -SRL (IX+n),r 4 0xdd,0xcb,0,0x38 idx_r8 Z80,R800 -SRL (IY+n),r 4 0xfd,0xcb,0,0x38 idx_r8 Z80,R800 +SRL (IX+n),r 4 0xdd,0xcb,0,0x38 idx Z80,R800 +SRL (IY+n),r 4 0xfd,0xcb,0,0x38 idx Z80,R800 # Bit manipulation group BIT imm3,r 2 0xcb,0x40 r_bit Z80,R800 diff --git a/as/target/z80/test.s b/as/target/z80/test.s @@ -488,29 +488,29 @@ INC %IXL / DD 2C DEC %IXL / DD 2D LD %IXL,64 / DD 2E 40 -/DD34 d INC (IX + d) -/DD35 d DEC (IX + d) -/DD36 d n LD (IX + d), n + INC (%IX + 32) / DD 34 20 + DEC (%IX + 16) / DD 35 10 + LD (%IX + 64),128 / DD 36 40 80 ADD %IX,%SP / DD 39 LD %B,%IXH / DD 44 LD %B,%IXL / DD 45 -/DD46 d LD B, (IX + d) + LD %B,(%IX + 32) / DD 46 20 LD %C,%IXH / DD 4C LD %C,%IXL / DD 4D -/DD4E d LD C, (IX + d) + LD %C,(%IX + 48) / DD 4E 30 LD %D,%IXH / DD 54 LD %D,%IXL / DD 55 -/DD56 d LD D, (IX + d) + LD %D,(%IX + 32) / DD 56 20 LD %E,%IXH / DD 5C LD %E,%IXL / DD 5D -/DD5E d LD E, (IX + d) + LD %E,(%IX + 64) / DD 5E 40 LD %IXH,%B / DD 60 LD %IXH,%C / DD 61 LD %IXH,%D / DD 62 LD %IXH,%E / DD 63 LD %IXH,%IXH / DD 64 LD %IXH,%IXL / DD 65 -/DD66 d LD H, (IX + d) + LD %H,(%IX + 16) / DD 66 10 LD %IXH,%A / DD 67 LD %IXL,%B / DD 68 LD %IXL,%C / DD 69 @@ -518,42 +518,42 @@ LD %IXL,%E / DD 6B LD %IXL,%IXH / DD 6C LD %IXL,%IXL / DD 6D -/DD6E d LD L, (IX + d) + LD %L,(%IX + 48) / DD 6E 30 LD %IXL,%A / DD 6F -/DD70 d LD (IX + d), B -/DD71 d LD (IX + d), C -/DD72 d LD (IX + d), D -/DD73 d LD (IX + d), E -/DD74 d LD (IX + d), H -/DD75 d LD (IX + d), L -/DD77 d LD (IX + d), A + LD (%IX + 64),%B / DD 70 40 + LD (%IX + 16),%C / DD 71 10 + LD (%IX + 32),%D / DD 72 20 + LD (%IX + 48),%E / DD 73 30 + LD (%IX + 16),%H / DD 74 10 + LD (%IX + 32),%L / DD 75 20 + LD (%IX + 48),%A / DD 77 30 LD %A,%IXH / DD 7C LD %A,%IXL / DD 7D -/DD7E d LD A, (IX + d) + LD %A,(%IX + 16) / DD 7E 10 ADD %A,%IXH / DD 84 ADD %A,%IXL / DD 85 -/DD86 d ADD A, (IX + d) + ADD %A,(%IX + 32) / DD 86 20 ADC %A,%IXH / DD 8C ADC %A,%IXL / DD 8D -/DD8E d ADC A, (IX + d) + ADC %A,(%IX + 48) / DD 8E 30 SUB %A,%IXH / DD 94 SUB %A,%IXL / DD 95 -/DD96 d SUB (IX + d) + SUB %A,(%IX + 16) / DD 96 10 SBC %A,%IXH / DD 9C SBC %A,%IXL / DD 9D -/DD9E d SBC A, (IX + d) + SBC %A,(%IX + 32) / DD 9E 20 AND %A,%IXH / DD A4 AND %A,%IXL / DD A5 -/DDA6 d AND (IX + d) + AND %A,(%IX + 48) / DD A6 30 XOR %A,%IXH / DD AC XOR %A,%IXL / DD AD -/DDAE d XOR (IX + d) + XOR %A,(%IX + 16) / DD AE 10 OR %A,%IXH / DD B4 OR %A,%IXL / DD B5 -/DDB6 d OR (IX + d) + OR %A,(%IX + 32) / DD B6 20 CP %A,%IXH / DD BC CP %A,%IXL / DD BD -/DDBE d CP (IX + d) + CP %A,(%IX + 48) / DD BE 30 /DDCB d 00 LD B, RLC (IX + d)* /DDCB d 01 LD C, RLC (IX + d)* /DDCB d 02 LD D, RLC (IX + d)* @@ -861,29 +861,29 @@ INC %IYL / FD 2C DEC %IYL / FD 2D LD %IYL,16 / FD 2E 10 -/FD34 d INC (IY + d) -/FD35 d DEC (IY + d) -/FD36 d n LD (IY + d), n + INC (%IY + 32) / FD 34 20 + DEC (%IY + 48) / FD 35 30 + LD (%IY + 64),16 / FD 36 40 10 ADD %IY,%SP / FD 39 LD %B,%IYH / FD 44 LD %B,%IYL / FD 45 -/FD46 d LD B, (IY + d) + LD %B,(%IY + 32) / FD 46 20 LD %C,%IYH / FD 4C LD %C,%IYL / FD 4D -/FD4E d LD C, (IY + d) + LD %C,(%IY + 48) / FD 4E 30 LD %D,%IYH / FD 54 LD %D,%IYL / FD 55 -/FD56 d LD D, (IY + d) + LD %D,(%IY + 64) / FD 56 40 LD %E,%IYH / FD 5C LD %E,%IYL / FD 5D -/FD5E d LD E, (IY + d) + LD %E,(%IY + 16) / FD 5E 10 LD %IYH,%B / FD 60 LD %IYH,%C / FD 61 LD %IYH,%D / FD 62 LD %IYH,%E / FD 63 LD %IYH,%IYH / FD 64 LD %IYH,%IYL / FD 65 -/FD66 d LD H, (IY + d) + LD %H,(%IY + 32) / FD 66 20 LD %IYH,%A / FD 67 LD %IYL,%B / FD 68 LD %IYL,%C / FD 69 @@ -891,42 +891,42 @@ LD %IYL,%E / FD 6B LD %IYL,%IYH / FD 6C LD %IYL,%IYL / FD 6D -/FD6E d LD L, (IY + d) + LD %L,(%IY + 48) / FD 6E 30 LD %IYL,%A / FD 6F -/FD70 d LD (IY + d), B -/FD71 d LD (IY + d), C -/FD72 d LD (IY + d), D -/FD73 d LD (IY + d), E -/FD74 d LD (IY + d), H -/FD75 d LD (IY + d), L -/FD77 d LD (IY + d), A + LD (%IY + 64),%B / FD 70 40 + LD (%IY + 16),%C / FD 71 10 + LD (%IY + 32),%D / FD 72 20 + LD (%IY + 48),%E / FD 73 30 + LD (%IY + 64),%H / FD 74 40 + LD (%IY + 16),%L / FD 75 10 + LD (%IY + 32),%A / FD 77 20 LD %A,%IYH / FD 7C LD %A,%IYL / FD 7D -/FD7E d LD A, (IY + d) + LD %A,(%IY + 48) / FD 7E 30 ADD %A,%IYH / FD 84 ADD %A,%IYL / FD 85 -/FD86 d ADD A, (IY + d) + ADD %A,(%IY + 64) / FD 86 40 ADC %A,%IYH / FD 8C ADC %A,%IYL / FD 8D -/FD8E d ADC A, (IY + d) + ADC %A,(%IY + 16) / FD 8E 10 SUB %A,%IYH / FD 94 SUB %A,%IYL / FD 95 -/FD96 d SUB (IY + d) + SUB %A,(%IY + 32) / FD 96 20 SBC %A,%IYH / FD 9C SBC %A,%IYL / FD 9D -/FD9E d SBC A, (IY + d) + SBC %A,(%IY + 48) / FD 9E 30 AND %A,%IYH / FD A4 AND %A,%IYL / FD A5 -/FDA6 d AND (IY + d) + AND %A,(%IY + 64) / FD A6 40 XOR %A,%IYH / FD AC XOR %A,%IYL / FD AD -/FDAE d XOR (IY + d) + XOR %A,(%IY + 16) / FD AE 10 OR %A,%IYH / FD B4 OR %A,%IYL / FD B5 -/FDB6 d OR (IY + d) + OR %A,(%IY + 32) / FD B6 20 CP %A,%IYH / FD BC CP %A,%IYL / FD BD -/FDBE d CP (IY + d) + CP %A,(%IY + 48) / FD BE 30 /FDCB d 00 LD B, RLC (IY + d)* /FDCB d 01 LD C, RLC (IY + d)* /FDCB d 02 LD D, RLC (IY + d)*